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Test your basic knowledge |
Digital Fundamentals
Start Test
Study First
Subject
:
engineering
Instructions:
Answer 50 questions in 15 minutes.
If you are not ready to take this test, you can
study here
.
Match each statement with the correct term.
Don't refresh. All questions and answers are randomly picked and ordered every time you load a test.
This is a study tool. The 3 wrong answers for each question are randomly chosen from answers to other questions. So, you might find at times the answers obvious, but you will see it re-enforces your understanding as you take the test each time.
1. A stage of the DSP pipeline operation in which instructions are assigned to functional units and are decoded.
Circuit
Base address
Decode
Boolean expression
2. To connect 'end- to- end' as when several counters are connected from the terminal count output of one counter to the enable input of the next counter
DMA
Cascade
AND gate
Digital linear tape
3. A group of eight bits
Balanced Bridge
Collector
AND gate
Byte
4. A binary digit - which can be either 1 or 0
Bus contention
Bit
ABEL(Advance Boolean Expression Language)
Digital linear tape
5. A type of magnetic tape format
Dual in - line package
Digital linear tape
Kirchoff's Current Law(KCL)
Bode Plot
6. A receiving device on a bus
Acceptor
Carry
Architecture
Charge- coupled device
7. A semiconductor device that conducts current in only one direction
Diode
Amplitude
Controller
Digital linear tape
8. Burst extended data output dynamic random- access memory
Clock
Bleeder Current
ANSI
BEDO DRAM
9. Information in numeric - alphabetic - or other form.
CPLD
Data
D Flip-Flop
Boolean multiplication
10. In addition (ORing) and multiplication (ANDing) of two variables the order in which the variables are ORed or ANDed makes no difference
AWG
Commutative Law
Carry
Apparent power
11. In a PLD - a matrix formed by rows of product- term lines columns of input lines with a programmable cell at each junctions. In VHDL - an array is an ordered set of individual items called elements with a single identifier name.
CLB (Configurable Logic Block)
Decrement
Array
Assembly language
12. Characteristic of cells in a Karnaugh map in which there is a single- variable change from one cell to another cell next to it on any of its four sides
Clock
Array
Adjacency
CMOS
13. A digital code in which each of the decimal digits - 0 through 9 - is represented by a group of four bits
Closed circuit
Charge- coupled device
Binary coded decimal
Bus interface unit
14. An adverse condition that could occur if two or more devices try to communicate at the same time on a bus
Delta Modulation
Acceptor
Bus contention
Dual in - line package
15. In addition - the number that is added to another number called the augend
Addend
Demultiplexer
CMOS Complementary Metal Oxide Semiconductor
Assembler
16. The beginning address of a segment of memory
Base address
Carry generation
bed- of- nails
Control Bus
17. Basic input/output system; a set of programs in ROM that interfaces the I/) devices in a computer system
Aliasing
Amplitude
Associative law
BIOS
18. A circuit that selects data from several inputs one at a time in a sequence and places them on the output; also called a multiplexer.
Data Selector
Cross - assembler
Data bus
ABEL(Advance Boolean Expression Language)
19. Having two values or states; describes a number system that has a base of two and utilizes 1 and 0 as its digits
Associative law
Control Unit
Addend
Binary
20. A circuit that prevents loading of an input or output
Average value
AND
Baseline
Buffer
21. The current left after the total load current is subtracted from the total current into the circuit
Bleeder Current
Combinational logic
Cross - assembler
Don't Care...
22. The opposition of a capacitor to permit current; the reciprocal of capacitive reactance. The unit is the siemens.
Capacitance Reactance
AND
Norton's Theorem
Bus interface unit
23. The actual current in a branch
Center Tap
Branch Current
Adder
Boundary scan
24. The location of a given storage cell or group of cells in a memory; a unique memory location containing on byte
Commutative Law
Balanced Bridge
Autotransformer
Address
25. The process of converting an analog signal to digital form
Analog- to- digital (A/D) conversion
Architecture
Component
Boolean multiplication
26. Having two opposites charge carriers within the transistor structure
Bipolar
Decimal
Antifuse
Byte
27. The law that states ORing several variables and then ANDing the single variable with each of the several variables and the ORing the product
Distributive Law
Circuit
Carry generation
DCE
28. The average of a sine wave over one half- cycle. It is 0.637 times the peak value.
Bleeder Current
Base
Control Unit
Average value
29. A combined coder and decoder
Code
Norton's Theorem
Combinational logic
Demultiplexer
30. The main part of a computer responsible for control and processing of data; the core of a DSP that processes the program instructions
Base
Bus contention
DRAM
Central processing unit
31. A circuit with a complete current path
ASCII
Data
Analog- to- digital converter(ADC)
Closed circuit
32. An electrical instrument used to measure current
Ammeter
Analog
Adjacency
Bus arbitration
33. A filter that rejects a range of frequencies lying between two critical frequencies and passes frequencies above and below that range.
Band- stop filter
Ampere
Commutative Law
Comparator
34. An arrangement of electrical and/or electronic components interconnected in such a way as to perform a specified function
Dependency notation
Circuit
Data
Bus
35. The unit of electrical current
Ampere
Angular Velocity
Attenuation
Complement
36. Characterized by ten states or values
AND array
Array
Control Bus
Decade
37. A type of semiconductor memory that stores data in the form of charge packets and is serially accessed
Controller
Bit time
Balanced Bridge
Charge- coupled device
38. A digital counter having ten states
Digital linear tape
Decade Counter
Control Bus
Bistable
39. A measure of the ability of a reactive circuit to permit current; the reciprocal of impedance. the unit is the siemens
Autotransformer
Admittance
Base
ASCII
40. American wire gauge; a standardization based on wire diameter
Carry
Decode
AWG
Charge
41. A connection at the midpoint of a winding in a transformer
Center Tap
Ampere
BEDO DRAM
D Flip-Flop
42. A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmable interconnect that is used to connect logic modules within the CLB
Assembly language
Component
Admittance
CLB (Configurable Logic Block)
43. A circuit (digital service) that switches digital data from one input line to several output lines in a specified time sequence
bed- of- nails
Data Selector
Demultiplexer
Balanced Load
44. The graph of a filter's frequency response showing the change in the output voltage to input voltage ratio expressed in dB as a function of frequency for a constant input voltage
Aliasing
Bode Plot
Decade
Decade Counter
45. The VHDL unit that describes the internal operation of a logic function; the internal functional arrangement of the elements that give a device its particular operating characteristics.
Data
Architecture
Acceptor
Bias
46. The process or sequence of operations carried out to program a target device
Capacitor
Bus arbitration
Design flow
Ammeter
47. A one- way group of conductors from the to a memory - or other external device - on which the address code is sent
Admittance
Controller
Norton's Theorem
Address Bus
48. The number of protons in a nucleus
Decimal
Norton's Theorem
Ampere
Atomic number
49. In a pulse waveform - the height or maximum value of the pulse as measured from its low level.
Control Bus
Astable
Amplitude
Ampere
50. The rotational rate of a phasor which is related to the frequency of the sine wave that the phasor represents
Clock
Angular Velocity
Bipolar
AND gate