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Test your basic knowledge |
Digital Fundamentals
Start Test
Study First
Subject
:
engineering
Instructions:
Answer 50 questions in 15 minutes.
If you are not ready to take this test, you can
study here
.
Match each statement with the correct term.
Don't refresh. All questions and answers are randomly picked and ordered every time you load a test.
This is a study tool. The 3 wrong answers for each question are randomly chosen from answers to other questions. So, you might find at times the answers obvious, but you will see it re-enforces your understanding as you take the test each time.
1. In addition (ORing) and multiplication (ANDing) of two variables the order in which the variables are ORed or ANDed makes no difference
Design flow
Commutative Law
AND array
Baseline
2. A method for internally testing a PLD based on the JTAG standard (IEEE std.)
Boundary scan
Admittance
Decade
Cache memory
3. The effect created when a signal is sampled at less than twice the signal frequency. Aliasing creates unwanted frequencies that interfere with the signal frequency.
Boolean multiplication
Aliasing
Antifuse
DSP
4. Having no stable state. An astable multivibrator oscillates between two quasi- stable states.
Astable
Cache memory
Central processing unit
Architecture
5. Information in numeric - alphabetic - or other form.
Data
Central processing unit
Cross - assembler
Bistable
6. A program that translates an assembly language program for one type of microprocessor to an assembly language for another type of microprocessor
Code
Cross - assembler
Diode
Dual in - line package
7. A digital circuit capable of counting electronic events - such as pulses - by progressing through a sequence of binary states.
Carry generation
ABEL(Advance Boolean Expression Language)
Balanced Bridge
Counter
8. In Boolean algebra - the AND operation
Architecture
Boolean multiplication
CPLD
Access time
9. A type of bistable multivibrator in which the output assumes the state of the D input on the triggering edge of a clock pulse.
Admittance
Branch
D Flip-Flop
Balanced Load
10. Sum of all the voltage drops in series equals to the source voltage
11. A binary digit - which can be either 1 or 0
Bit
Access time
CLB (Configurable Logic Block)
Vx=(Vs * Rx) /RT
12. An instrument that can specify each of the other instruments on the bus as either a talker or a listener for the purpose of data transfer.
DMA
Complement
Bistable
Controller
13. To decrease the binary state of a counter by one
Decrement
Analog
Base
Bistable
14. The application of a dc voltage to an electronic device to produce a desired mode of operation
Norton's Theorem
Bias
Analog
Commutative Law
15. Burst extended data output dynamic random- access memory
Data bus
Acceptor
Ammeter
BEDO DRAM
16. Basic input/output system; a set of programs in ROM that interfaces the I/) devices in a computer system
BIOS
AND
Balanced Bridge
ANSI
17. A type of semiconductor memory having capacitive storage cells that lose stored data over a period of time and therefore must be refreshed.
Circuit
Dynamic Memory
Boolean algebra
Aliasing
18. The ratio of pulse width to period expressed as a percentage
Amplitude
Baseline
Decade
Duty cycle
19. A digital counter having ten states
Decade Counter
DAT
Bandwidth
Baseline
20. An adverse condition that could occur if two or more devices try to communicate at the same time on a bus
AND array
DMA
Bus contention
Boundary scan
21. A receiving device on a bus
Bleeder Current
Thevenin Equivalent Circuit
Acceptor
Norton's Theorem
22. A circuit (digital service) that switches digital data from one input line to several output lines in a specified time sequence
Decade
Demultiplexer
Charge
Carry propagation
23. A logic circuit used to add two binary numbers
Control Bus
Decrement
Digital linear tape
Adder
24. Stands for Complementary Metal-Oxide Semiconductor and is implemented with a type of field transistor
Analog- to- digital (A/D) conversion
Bus interface unit
CMOS
Circular Mil (CM)
25. The number of protons in a nucleus
Current sinking
Atomic number
Baseline
Bistable
26. A type of inductor used to block or choke off high frequencies
Amplitude
D Flip-Flop
Comparator
Choke
27. The total number of data units(bits - nibbles - bytes - words) that a memory can store.
Kirchoff's Current Law(KCL)
Digital linear tape
Capacity
Center Tap
28. An arrangement of electrical and/or electronic components interconnected in such a way as to perform a specified function
Charge- coupled device
Alphanumeric
Circuit
Compiler
29. A type of PLD nonvolatile programmable link that can be left open or can be shorted once as directed by the program
Band- pass filter
Delta Modulation
Combinational logic
Antifuse
30. A condition where all the load currents are equal and the neutral current is zero
Balanced Load
ALU
ANSI
Decade
31. A connection at the midpoint of a winding in a transformer
Bias
Bus arbitration
Vx=(Vs * Rx) /RT
Center Tap
32. A VHDL feature that can be used to predefine the logic function for multiple use throughout a program or programs
Carry generation
Component
Boolean expression
Distributive Law
33. A method of analog- to- digital conversion using a 1- bit quantization process
CLB (Configurable Logic Block)
Bidirectional shift Register
Base
Delta Modulation
34. The average of a sine wave over one half- cycle. It is 0.637 times the peak value.
Average value
Binary
Compiler
ALU
35. In addition (Oring) and multiplication (ANDing) of three or more variables - the order in which the variables are grouped makes no difference
Average value
Assembly language
Aliasing
Associative law
36. The main part of a computer responsible for control and processing of data; the core of a DSP that processes the program instructions
Central processing unit
Decrement
Atom
Addend
37. An array of AND gates consisting of a matrix of programmable interconnection
Distributive Law
AND
AND array
Apparent power
38. A digital code in which each of the decimal digits - 0 through 9 - is represented by a group of four bits
Byte
Thevenin Equivalent Circuit
Dividend
Binary coded decimal
39. A type of IC package whose leads must pass through holes to the other side of a PC board
Capacitor
Astable
Buffer
Dual in - line package
40. An application program in development software packages that controls the design flow process and translates source code into object code in a format that can be logically tested or downloaded to a target device
Apparent power
AND
Compiler
AND gate
41. A measure of the ability of a reactive circuit to permit current; the reciprocal of impedance. the unit is the siemens
BEDO DRAM
Admittance
Amplitude
Carry generation
42. A transformer in which the primary and secondary are in a single winding
Data Selector
Bistable
Cascade
Autotransformer
43. Having two stable states. Flip- flops and latches are bistable multivibrators.
DIMM
Assembler
Bistable
Decrement
44. The unit of electrical current
Aliasing
Carry generation
Ampere
BIOS
45. A digital circuit that compares the magnitudes of two quantiities and produces an output indicating the relationship of the quantities
Ammeter
Bidirectional shift Register
Boolean expression
Comparator
46. In a pulse waveform - the height or maximum value of the pulse as measured from its low level.
Bus interface unit
Atomic number
Amplitude
Decoder
47. Having two values or states; describes a number system that has a base of two and utilizes 1 and 0 as its digits
Collector
Controller
Binary
Bitstream
48. American Standard Code for Information Interchange; the most widely used alphanumeric code.
Adjacency
Associative law
CPLD
ASCII
49. The time from the application of a valid memory address to the appearance of valid output data
DIMM
Access time
DSP
Baseline
50. American wire gauge; a standardization based on wire diameter
AWG
Dynamic Memory
Choke
Closed circuit