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Test your basic knowledge |
Digital Fundamentals
Start Test
Study First
Subject
:
engineering
Instructions:
Answer 50 questions in 15 minutes.
If you are not ready to take this test, you can
study here
.
Match each statement with the correct term.
Don't refresh. All questions and answers are randomly picked and ordered every time you load a test.
This is a study tool. The 3 wrong answers for each question are randomly chosen from answers to other questions. So, you might find at times the answers obvious, but you will see it re-enforces your understanding as you take the test each time.
1. The action of a circuit in which it accepts current into its output from a load
Capacitance Reactance
Current sinking
Debug
Analog
2. Having two directions. the stored data can be shifted right or left
Bidirectional shift Register
Component
AHDL
Data Selector
3. A basic logic operation in which a true(high) output occurs only when all the input conditions are true (high)
Amplitude
Architecture
Assembly language
AND
4. To connect 'end- to- end' as when several counters are connected from the terminal count output of one counter to the enable input of the next counter
Antifuse
Band- pass filter
Asynchronous counter
Cascade
5. American wire gauge; a standardization based on wire diameter
Bus interface unit
Assembler
AWG
Code
6. In a pulse waveform - the height or maximum value of the pulse as measured from its low level.
AND
Design flow
Amplitude
Closed circuit
7. A type of PLD nonvolatile programmable link that can be left open or can be shorted once as directed by the program
Code
Antifuse
Carry propagation
Concurrency
8. An energy source that uses a chemical reaction to convert chemical energy into electrical energy.
Counter
Dividend
Average value
Battery
9. A code within DOS that allows various operations on files and includes a primitive assembler; to eliminate a problem in hardware or software.
Debug
Decade Counter
Decrement
BEDO DRAM
10. An instrument that can specify each of the other instruments on the bus as either a talker or a listener for the purpose of data transfer.
Controller
Boolean algebra
DRAM
CPLD
11. Characteristic of cells in a Karnaugh map in which there is a single- variable change from one cell to another cell next to it on any of its four sides
Adjacency
Binary coded decimal
DMA
ASCII
12. In relation to VHDL feature that permits operations to be processed in a parallel;that is operations that occur simultaneously
Concurrency
Counter
Bias
Comparator
13. A nominally continuous electrical signal that varies in amplitude or frequency in response to changes in sound - light - heat - position - or pressure.
Base address
Analog
Control Unit
Combinational logic
14. A type of IC package whose leads must pass through holes to the other side of a PC board
Complement
Dual in - line package
Bus interface unit
Component
15. Data Communications equipment
DCE
DAT
Central processing unit
AWG
16. A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmable interconnect that is used to connect logic modules within the CLB
CLB (Configurable Logic Block)
Assembler
Atomic number
Branch
17. The unit of electrical current
Component
Alphanumeric
Ampere
Bit
18. The beginning address of a segment of memory
Control Bus
DAT
Base address
AWG
19. A document that specifies parameter values and operating conditions for an integrated circuits or other device
D Flip-Flop
Decode
Boolean multiplication
Data Sheet
20. A circuit (digital service) that switches digital data from one input line to several output lines in a specified time sequence
Balanced Bridge
Attenuation
Clock
Demultiplexer
21. Information in numeric - alphabetic - or other form.
AHDL
Decode
Ampere- hour(Ah) rating
Data
22. Having no stable state. An astable multivibrator oscillates between two quasi- stable states.
Amplitude
Data bus
Astable
Debug
23. The opposition of a capacitor to permit current; the reciprocal of capacitive reactance. The unit is the siemens.
bed- of- nails
Capacitance Reactance
Cross - assembler
Admittance
24. A type of semiconductor memory having capacitive storage cells that lose stored data over a period of time and therefore must be refreshed.
Dynamic Memory
Concurrency
Bistable
Data bus
25. Digital Signal Processor; a special type of microprocessor that processes data in real time
Concurrency
Control Unit
DSP
bed- of- nails
26. A program that converts English- like mnemonics into machine code
Assembler
Dynamic Memory
BEDO DRAM
Decade
27. Describes a number system with a base of ten
Analog
AND gate
Decimal
ABEL(Advance Boolean Expression Language)
28. The VHDL unit that describes the internal operation of a logic function; the internal functional arrangement of the elements that give a device its particular operating characteristics.
Architecture
Control Unit
Debug
Bias
29. Dynamic random- access memory; a type of semiconductor memory that uses capacitors as the storage elements and is a volatile - read/write memory
Balanced Load
DRAM
Assembler
Balanced Bridge
30. An expression of variables and operators used to express the operation of a logic circuit
Diode
Branch
Boolean expression
Analog
31. A unit of the cross - sectional area of a wire.
Decimal
Carry
Admittance
Circular Mil (CM)
32. One of the three regions in a bipolar junction transistor
Associative law
Decimal
Decade
Base
33. Data Terminal equipment
Analog- to- digital converter(ADC)
DTE
Vx=(Vs * Rx) /RT
BEDO DRAM
34. Bipolar junction transistor; a semiconductor device used for switching or amplification. A BJT has two junctions - the base- emitter junction and the base- collector junction
AWG
BJT
Adjacency
BEDO DRAM
35. Altera HDL; a nonstandard HDL
AHDL
Bitstream
Ampere- hour(Ah) rating
Balanced Bridge
36. A stage of the DSP pipeline operation in which instructions are assigned to functional units and are decoded.
Decode
Astable
Bandwidth
Thevenin Equivalent Circuit
37. The ability of a capacitor to store electrical charge.
Bistable
Capacitance
CPLD
Apparent power
38. A digital circuit capable of counting electronic events - such as pulses - by progressing through a sequence of binary states.
Counter
Bus arbitration
CMOS
CPLD
39. A semiconductor device that conducts current in only one direction
Cache memory
Diode
ASCII
Bandwidth
40. A logic gate that produces a High output only when all of the inputs are HIGH
Branch Current
Clear
AND gate
Central processing unit
41. The process of converting an analog signal to digital form
Complement
Control Bus
Analog- to- digital (A/D) conversion
Bus arbitration
42. A set of interconnections that interface one or more devices based on a standardized specification
DSP
Buffer
Average value
Bus
43. The maximum value of a voltage or current
Boolean multiplication
Demultiplexer
CMOS Complementary Metal Oxide Semiconductor
Amplitude
44. The mathematics of logic circuits
Bus interface unit
Decoder
Carry generation
Boolean algebra
45. An array of AND gates consisting of a matrix of programmable interconnection
Kirchoff's Current Law(KCL)
Branch
Decade
AND array
46. In addition - the number to which the addend is added
Augend
Ammeter
Boolean expression
Dual in - line package
47. Having two values or states; describes a number system that has a base of two and utilizes 1 and 0 as its digits
DTE
Binary
Diode
Component
48. A series of bits describing a final design that is sent to the target device during programming
Choke
Access time
Center Tap
Bitstream
49. A relatively small - high- speed memory that stores the most recently used instructions or data from the larger but slower main memory
Kirchoff's Current Law(KCL)
Dependency notation
DCE
Cache memory
50. To decrease the binary state of a counter by one
Decade
Decrement
Associative law
Capacitance Reactance