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Test your basic knowledge |
Digital Fundamentals
Start Test
Study First
Subject
:
engineering
Instructions:
Answer 50 questions in 15 minutes.
If you are not ready to take this test, you can
study here
.
Match each statement with the correct term.
Don't refresh. All questions and answers are randomly picked and ordered every time you load a test.
This is a study tool. The 3 wrong answers for each question are randomly chosen from answers to other questions. So, you might find at times the answers obvious, but you will see it re-enforces your understanding as you take the test each time.
1. In addition - the number that is added to another number called the augend
Branch
Dependency notation
Addend
Controller
2. The effect created when a signal is sampled at less than twice the signal frequency. Aliasing creates unwanted frequencies that interfere with the signal frequency.
Bleeder Current
Aliasing
Boolean algebra
Capacitance Reactance
3. A logic circuit used to add two binary numbers
CMOS
Adder
Combinational logic
Center Tap
4. An energy source that uses a chemical reaction to convert chemical energy into electrical energy.
Don't Care...
Autotransformer
Controller
Battery
5. The location of a given storage cell or group of cells in a memory; a unique memory location containing on byte
Admittance
Charge- coupled device
Address
Aliasing
6. The actual current in a branch
Branch Current
Vx=(Vs * Rx) /RT
Adder
Acceptor
7. American wire gauge; a standardization based on wire diameter
AWG
Control Bus
Component
Concurrency
8. A group of eight bits
ABEL(Advance Boolean Expression Language)
Bus
Byte
Code
9. Having two values or states; describes a number system that has a base of two and utilizes 1 and 0 as its digits
Boolean multiplication
Battery
Binary
Byte
10. In relation to VHDL feature that permits operations to be processed in a parallel;that is operations that occur simultaneously
Atom
Bandwidth
Concurrency
Autotransformer
11. A transformer in which the primary and secondary are in a single winding
Concurrency
Alphanumeric
Angular Velocity
Autotransformer
12. A type of magnetic tape format
ALU
Data Sheet
Digital linear tape
Cache memory
13. A electrical property of matter that exist because of an excess or a deficiency of electrons. Can be either positive or negative
ALU
Charge
Array
Carry
14. A bidirectional set of conductive paths on which data or instruction codes are transferred into a microprocessor or on which the result of an operation is sent out from the microprocessor
Decrement
Circular Mil (CM)
Data bus
BJT
15. In a PLD - a matrix formed by rows of product- term lines columns of input lines with a programmable cell at each junctions. In VHDL - an array is an ordered set of individual items called elements with a single identifier name.
AWG
Array
Decoder
Concurrency
16. The ratio of pulse width to period expressed as a percentage
Asynchronous counter
Analog- to- digital converter(ADC)
Duty cycle
Cross - assembler
17. A one- way group of conductors from the to a memory - or other external device - on which the address code is sent
Decrement
Address Bus
Bleeder Current
Adjacency
18. An array of AND gates consisting of a matrix of programmable interconnection
Bitstream
AND array
Design flow
AHDL
19. A VHDL feature that can be used to predefine the logic function for multiple use throughout a program or programs
Asynchronous counter
Digital linear tape
Component
Cache memory
20. A notational system for logic symbols that specifies input and output relationships thus fully defining a given function
Boolean algebra
Concurrency
Assembler
Dependency notation
21. The process that prevents two sources from using a bus at the same time
Current sinking
Bus arbitration
Concurrency
Carry propagation
22. A theorem that states that any amount of voltage sources and current sources can be combined into a single current source with a parallel resistor.
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183
23. A set of interconnections that interface one or more devices based on a standardized specification
Boolean algebra
Bus
Adjacency
Bit time
24. A reduction of the output signal compared to the input signal - resulting in a ratio with a value of less than 1 for the output voltage to the input voltage of a circuit.
Thevenin Equivalent Circuit
Amplitude
Attenuation
Circuit
25. Burst extended data output dynamic random- access memory
Branch
ASCII
Bit
BEDO DRAM
26. A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmable interconnect that is used to connect logic modules within the CLB
Data bus
AWG
Address
CLB (Configurable Logic Block)
27. An expression of variables and operators used to express the operation of a logic circuit
Cross - assembler
Capacitor
BIOS
Boolean expression
28. The maximum value of a voltage or current
DIMM
Amplitude
AND array
Capacitance Reactance
29. A circuit that prevents loading of an input or output
Code
Ampere- hour(Ah) rating
Bias
Buffer
30. The process of converting an analog signal to digital form
Circuit
Analog- to- digital converter(ADC)
Analog- to- digital (A/D) conversion
Assembler
31. Having no stable state. An astable multivibrator oscillates between two quasi- stable states.
CLB (Configurable Logic Block)
Astable
Current sinking
Decade
32. The rotational rate of a phasor which is related to the frequency of the sine wave that the phasor represents
Angular Velocity
AND array
Alphanumeric
Admittance
33. A type of inductor used to block or choke off high frequencies
Kirchoff's Voltage Law
Choke
Associative law
Acceptor
34. The law that states ORing several variables and then ANDing the single variable with each of the several variables and the ORing the product
Atomic number
Diode
Carry propagation
Distributive Law
35. The current left after the total load current is subtracted from the total current into the circuit
Dividend
ASCII
Bleeder Current
Dynamic Memory
36. A type of semiconductor memory having capacitive storage cells that lose stored data over a period of time and therefore must be refreshed.
Dynamic Memory
Associative law
Duty cycle
Boundary scan
37. A filter that rejects a range of frequencies lying between two critical frequencies and passes frequencies above and below that range.
Battery
Band- stop filter
Address
bed- of- nails
38. The range of frequencies for which the current (or output voltage) is equal to or greater than 70.7% of its value at the resonant frequency that is considered to be passed by a filter.
Bandwidth
Distributive Law
Balanced Load
DCE
39. To decrease the binary state of a counter by one
Binary
Diode
Decrement
Address Bus
40. Stands for Complementary Metal-Oxide Semiconductor and is implemented with a type of field transistor
CMOS
Design flow
Binary coded decimal
Collector
41. A number given in ampere- hours determined by multiplying the current times the length of the time (h) a battery can deliver that current to a load
Alphanumeric
Average value
Ampere- hour(Ah) rating
Bidirectional shift Register
42. The process of producing an output carry in full- adder when both input bits are 1s.
Bipolar
Carry generation
Boundary scan
Angular Velocity
43. The number of protons in a nucleus
AND array
Atomic number
ALU
Array
44. The interval of time occupied by a single bit in a sequence of bits; the period of the clock
Carry
Ammeter
DCE
Bit time
45. One of the three regions in a bipolar junction transistor
Base
Boolean addition
DTE
Bistable
46. One current path in a parallel circuit; a current path that connects two nodes
Dividend
Atom
Branch
Carry propagation
47. A basic logic operation in which a true(high) output occurs only when all the input conditions are true (high)
Charge
AND
DMA
Data
48. An adverse condition that could occur if two or more devices try to communicate at the same time on a bus
Bipolar
Comparator
Bus contention
Closed circuit
49. The ability of a capacitor to store electrical charge.
Address Bus
Bias
Bus interface unit
Capacitance
50. A combination of logic gates interconnected to produce a specified Boolean function with no storage or memory capability; sometimes called combinatorial logic
Ampere- hour(Ah) rating
Augend
Combinational logic
Analog- to- digital converter(ADC)
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