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Test your basic knowledge |
Digital Fundamentals
Start Test
Study First
Subject
:
engineering
Instructions:
Answer 50 questions in 15 minutes.
If you are not ready to take this test, you can
study here
.
Match each statement with the correct term.
Don't refresh. All questions and answers are randomly picked and ordered every time you load a test.
This is a study tool. The 3 wrong answers for each question are randomly chosen from answers to other questions. So, you might find at times the answers obvious, but you will see it re-enforces your understanding as you take the test each time.
1. A bridge circuit that is in the balanced state as indicated by 0 V across the output.
Choke
Control Unit
Balanced Bridge
DIMM
2. A circuit that prevents loading of an input or output
Buffer
Average value
Address Bus
Balanced Bridge
3. Describes a number system with a base of ten
Decimal
Bode Plot
Balanced Bridge
Data bus
4. Having two directions. the stored data can be shifted right or left
Bidirectional shift Register
Circular Mil (CM)
Debug
CMOS Complementary Metal Oxide Semiconductor
5. A method for the automated testing of printed circuit boards in which the board is mounted on a fixture that resembles a bed of nails that makes contact with test points
Current sinking
ANSI
bed- of- nails
Closed circuit
6. Having two values or states; describes a number system that has a base of two and utilizes 1 and 0 as its digits
Atom
Addend
Analog- to- digital (A/D) conversion
Binary
7. Burst extended data output dynamic random- access memory
BEDO DRAM
Don't Care...
Compiler
Autotransformer
8. A receiving device on a bus
Design flow
Acceptor
Analog- to- digital (A/D) conversion
Augend
9. Consisting of numerals - letters - and other characters
Band- pass filter
Amplitude
Alphanumeric
Access time
10. A two terminal circuit containing voltage sources - current sources - and resistors can be modeled as a voltage source in series with a resistor
ABEL(Advance Boolean Expression Language)
Thevenin Equivalent Circuit
bed- of- nails
Boundary scan
11. The ratio of pulse width to period expressed as a percentage
Dual in - line package
BEDO DRAM
Commutative Law
Duty cycle
12. In Boolean algebra - the AND operation
Circuit
Bus contention
Boolean multiplication
Average value
13. A program that translates an assembly language program for one type of microprocessor to an assembly language for another type of microprocessor
Autotransformer
Cross - assembler
BEDO DRAM
CPLD
14. Basic input/output system; a set of programs in ROM that interfaces the I/) devices in a computer system
Asynchronous counter
Bias
BIOS
Carry
15. A series of bits describing a final design that is sent to the target device during programming
Dependency notation
Bitstream
Current sinking
Apparent power
16. The normal level of a pulse waveform; the voltage level in the absence of a pulse.
Baseline
Bitstream
Bus arbitration
CPLD
17. Having two stable states. Flip- flops and latches are bistable multivibrators.
Bistable
Norton's Theorem
CMOS
Cross - assembler
18. An arrangement of electrical and/or electronic components interconnected in such a way as to perform a specified function
Circuit
Boolean multiplication
Base
DSP
19. A code within DOS that allows various operations on files and includes a primitive assembler; to eliminate a problem in hardware or software.
Circular Mil (CM)
Bistable
Bus interface unit
Debug
20. The rotational rate of a phasor which is related to the frequency of the sine wave that the phasor represents
Diode
Boolean multiplication
Angular Velocity
Admittance
21. Sum of all currents entering a node is equal to the sum of all currents leaving the same node
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22. A software compiler language for SPLD programming; a type of hardware description language (HDL)
ABEL(Advance Boolean Expression Language)
Capacitor
Decade Counter
Circuit
23. A type of counter in which each stage is clocked from the output of the preceding stage.
Debug
Atom
Decade
Asynchronous counter
24. A stage of the DSP pipeline operation in which instructions are assigned to functional units and are decoded.
Augend
Angular Velocity
DIMM
Decode
25. A electrical property of matter that exist because of an excess or a deficiency of electrons. Can be either positive or negative
Charge
Capacity
Average value
bed- of- nails
26. A digital circuit that compares the magnitudes of two quantiities and produces an output indicating the relationship of the quantities
Capacitance Reactance
Control Unit
Comparator
Dual in - line package
27. A semiconductor device that conducts current in only one direction
Diode
CLB (Configurable Logic Block)
Carry generation
Branch Current
28. An energy source that uses a chemical reaction to convert chemical energy into electrical energy.
Duty cycle
ALU
Battery
Control Bus
29. The portion within the microprocessor that provides the timing and control signals for getting data into and out of the microprocessor and for synchronizing the execution of instructions.
BEDO DRAM
Control Unit
Carry generation
Atomic number
30. The main part of a computer responsible for control and processing of data; the core of a DSP that processes the program instructions
Kirchoff's Current Law(KCL)
Aliasing
Bode Plot
Central processing unit
31. A notational system for logic symbols that specifies input and output relationships thus fully defining a given function
Atom
DAT
Boolean addition
Dependency notation
32. Information in numeric - alphabetic - or other form.
Array
Alphanumeric
Data
Adjacency
33. A type of IC package whose leads must pass through holes to the other side of a PC board
Amplitude
Boolean multiplication
Carry
Dual in - line package
34. In a pulse waveform - the height or maximum value of the pulse as measured from its low level.
Byte
Amplitude
D Flip-Flop
Balanced Bridge
35. A set of conductive paths hat connects the CPU to other parts of the computer to coordinate its operations and to communicate with external devices
AND
ABEL(Advance Boolean Expression Language)
Controller
Control Bus
36. Digital audio tape; a type of magnetic tape format
DAT
Distributive Law
Addend
Capacitance Reactance
37. A bidirectional set of conductive paths on which data or instruction codes are transferred into a microprocessor or on which the result of an operation is sent out from the microprocessor
Data bus
Analog- to- digital converter(ADC)
Band- pass filter
Decade
38. Having two opposites charge carriers within the transistor structure
Duty cycle
Bipolar
Balanced Load
Aliasing
39. An expression of variables and operators used to express the operation of a logic circuit
Clear
Boolean algebra
Boolean expression
Bode Plot
40. A combination of input literals that cannot occur and can be used as a 1 or 0 on a Karnaugh Map for simplification
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41. A theorem that states that any amount of voltage sources and current sources can be combined into a single current source with a parallel resistor.
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42. In relation to VHDL feature that permits operations to be processed in a parallel;that is operations that occur simultaneously
Amplitude
Atom
DAT
Concurrency
43. The average of a sine wave over one half- cycle. It is 0.637 times the peak value.
Dynamic Memory
Carry generation
Average value
Augend
44. Data Terminal equipment
DTE
Current sinking
Cascade
Circuit
45. The ability of a capacitor to store electrical charge.
Bus contention
Asynchronous counter
Capacitance
Average value
46. A type of bistable multivibrator in which the output assumes the state of the D input on the triggering edge of a clock pulse.
Balanced Load
D Flip-Flop
Apparent power
Alphanumeric
47. The number of protons in a nucleus
Autotransformer
Atomic number
Cache memory
BIOS
48. In a PLD - a matrix formed by rows of product- term lines columns of input lines with a programmable cell at each junctions. In VHDL - an array is an ordered set of individual items called elements with a single identifier name.
DRAM
ALU
Array
Thevenin Equivalent Circuit
49. An asynchronous input used to reset a flip- flop (make the Q output 0); to place a register or counter in the state in which it contains all 0's
Augend
Closed circuit
Antifuse
Clear
50. A complex programmable logic device that consists basically of muliple SPLD arrays with programmable interconnections.
CPLD
Code
Design flow
Comparator