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Digital Fundamentals

Subject : engineering
Instructions:
  • Answer 50 questions in 15 minutes.
  • If you are not ready to take this test, you can study here.
  • Match each statement with the correct term.
  • Don't refresh. All questions and answers are randomly picked and ordered every time you load a test.

This is a study tool. The 3 wrong answers for each question are randomly chosen from answers to other questions. So, you might find at times the answers obvious, but you will see it re-enforces your understanding as you take the test each time.
1. The law that states ORing several variables and then ANDing the single variable with each of the several variables and the ORing the product






2. Having no stable state. An astable multivibrator oscillates between two quasi- stable states.






3. Characteristic of cells in a Karnaugh map in which there is a single- variable change from one cell to another cell next to it on any of its four sides






4. In addition (ORing) and multiplication (ANDing) of two variables the order in which the variables are ORed or ANDed makes no difference






5. A filter that passes a range of frequencies lying between two critical freqencies and rejects frequencies above and below that range.






6. An adverse condition that could occur if two or more devices try to communicate at the same time on a bus






7. To connect 'end- to- end' as when several counters are connected from the terminal count output of one counter to the enable input of the next counter






8. A filter that rejects a range of frequencies lying between two critical frequencies and passes frequencies above and below that range.






9. American National Standards Institute






10. A method for the automated testing of printed circuit boards in which the board is mounted on a fixture that resembles a bed of nails that makes contact with test points






11. A receiving device on a bus






12. The process of rippling an input carry to become the output carry in a full- adder when either or both of the input bits are 1's and the input carry is a 1






13. A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmable interconnect that is used to connect logic modules within the CLB






14. The graph of a filter's frequency response showing the change in the output voltage to input voltage ratio expressed in dB as a function of frequency for a constant input voltage






15. A group of eight bits






16. A circuit (digital service) that switches digital data from one input line to several output lines in a specified time sequence






17. Sum of all the voltage drops in series equals to the source voltage

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18. A combination of input literals that cannot occur and can be used as a 1 or 0 on a Karnaugh Map for simplification

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19. An energy source that uses a chemical reaction to convert chemical energy into electrical energy.






20. A type of inductor used to block or choke off high frequencies






21. Direct memory access; a method to directly interface a peripheral device to memory without using the CPU for control






22. A circuit with a complete current path






23. A set of interconnections that interface one or more devices based on a standardized specification






24. A logic circuit used to add two binary numbers






25. An electrical device consisting of two conductive plates separated by an insulating material and possessing the property of capacitance.






26. A program that converts English- like mnemonics into machine code






27. In addition (Oring) and multiplication (ANDing) of three or more variables - the order in which the variables are grouped makes no difference






28. The opposition of a capacitor to permit current; the reciprocal of capacitive reactance. The unit is the siemens.






29. Stands for Complementary Metal-Oxide Semiconductor and is implemented with a type of field transistor






30. A resettable protective device used for interrupting execessive current in an electric circuit






31. The range of frequencies for which the current (or output voltage) is equal to or greater than 70.7% of its value at the resonant frequency that is considered to be passed by a filter.






32. Dynamic random- access memory; a type of semiconductor memory that uses capacitors as the storage elements and is a volatile - read/write memory






33. Consisting of numerals - letters - and other characters






34. A method for internally testing a PLD based on the JTAG standard (IEEE std.)






35. Burst extended data output dynamic random- access memory






36. A type of IC package whose leads must pass through holes to the other side of a PC board






37. The actual current in a branch






38. An instrument that can specify each of the other instruments on the bus as either a talker or a listener for the purpose of data transfer.






39. The portion of the CPU that interfaces with the system buses and fetches instructions - reads operands - and writes results.






40. The VHDL unit that describes the internal operation of a logic function; the internal functional arrangement of the elements that give a device its particular operating characteristics.






41. A software compiler language for SPLD programming; a type of hardware description language (HDL)






42. A connection at the midpoint of a winding in a transformer






43. Basic input/output system; a set of programs in ROM that interfaces the I/) devices in a computer system






44. Having two values or states; describes a number system that has a base of two and utilizes 1 and 0 as its digits






45. Data Terminal equipment






46. The main part of a computer responsible for control and processing of data; the core of a DSP that processes the program instructions






47. A digital circuit device that converts coded information into another (familiar) or noncoded form






48. A stage of the DSP pipeline operation in which instructions are assigned to functional units and are decoded.






49. The process of converting an analog signal to digital form






50. A type of bistable multivibrator in which the output assumes the state of the D input on the triggering edge of a clock pulse.