SUBJECTS
|
BROWSE
|
CAREER CENTER
|
POPULAR
|
JOIN
|
LOGIN
Business Skills
|
Soft Skills
|
Basic Literacy
|
Certifications
About
|
Help
|
Privacy
|
Terms
|
Email
Search
Test your basic knowledge |
Digital Fundamentals
Start Test
Study First
Subject
:
engineering
Instructions:
Answer 50 questions in 15 minutes.
If you are not ready to take this test, you can
study here
.
Match each statement with the correct term.
Don't refresh. All questions and answers are randomly picked and ordered every time you load a test.
This is a study tool. The 3 wrong answers for each question are randomly chosen from answers to other questions. So, you might find at times the answers obvious, but you will see it re-enforces your understanding as you take the test each time.
1. Consisting of numerals - letters - and other characters
Associative law
Addend
Baseline
Alphanumeric
2. The maximum value of a voltage or current
Kirchoff's Voltage Law
Amplitude
Array
Apparent power
3. A theorem that states that any amount of voltage sources and current sources can be combined into a single current source with a parallel resistor.
Warning
: Invalid argument supplied for foreach() in
/var/www/html/basicversity.com/show_quiz.php
on line
183
4. A condition where all the load currents are equal and the neutral current is zero
Balanced Load
Antifuse
Autotransformer
Vx=(Vs * Rx) /RT
5. The basic timing signal in a digital system; a periodic waveform in which the interval between pulses equals the time for one bit; the triggering input of a flip- flop
Concurrency
Circuit Breaker
Clock
Bus arbitration
6. The total number of data units(bits - nibbles - bytes - words) that a memory can store.
Capacity
Clock
Boolean algebra
Circuit Breaker
7. A filter that rejects a range of frequencies lying between two critical frequencies and passes frequencies above and below that range.
Analog
Binary
Band- stop filter
Average value
8. In relation to VHDL feature that permits operations to be processed in a parallel;that is operations that occur simultaneously
Dynamic Memory
Concurrency
Bit
DMA
9. Arithmetic Logic Unit; the key processing element of a microprocessor that perfoms arithmetic and logic operations.
Dividend
CLB (Configurable Logic Block)
Debug
ALU
10. The current left after the total load current is subtracted from the total current into the circuit
ABEL(Advance Boolean Expression Language)
Data bus
Bleeder Current
Average value
11. The main part of a computer responsible for control and processing of data; the core of a DSP that processes the program instructions
Branch Current
DIMM
Central processing unit
Kirchoff's Voltage Law
12. A combination of input literals that cannot occur and can be used as a 1 or 0 on a Karnaugh Map for simplification
Warning
: Invalid argument supplied for foreach() in
/var/www/html/basicversity.com/show_quiz.php
on line
183
13. A resettable protective device used for interrupting execessive current in an electric circuit
Circuit Breaker
DCE
ANSI
BIOS
14. The digit generated when the sum of two binary digits exceeds 1
Design flow
DRAM
Data bus
Carry
15. An adverse condition that could occur if two or more devices try to communicate at the same time on a bus
Bit
Debug
Combinational logic
Bus contention
16. Dual in - line memory module
Bit time
Control Unit
DIMM
BIOS
17. A type of counter in which each stage is clocked from the output of the preceding stage.
Asynchronous counter
Decade
Circuit
Decade Counter
18. The location of a given storage cell or group of cells in a memory; a unique memory location containing on byte
DTE
BIOS
Address
AWG
19. A digital circuit capable of counting electronic events - such as pulses - by progressing through a sequence of binary states.
Carry generation
Counter
Vx=(Vs * Rx) /RT
Circuit Breaker
20. An array of AND gates consisting of a matrix of programmable interconnection
Average value
Band- pass filter
AND gate
AND array
21. American wire gauge; a standardization based on wire diameter
Dynamic Memory
Bus interface unit
AWG
Boolean multiplication
22. The ratio of pulse width to period expressed as a percentage
Duty cycle
Architecture
BJT
AHDL
23. Having two stable states. Flip- flops and latches are bistable multivibrators.
Bidirectional shift Register
Bit
Balanced Load
Bistable
24. A one- way group of conductors from the to a memory - or other external device - on which the address code is sent
Counter
Branch Current
Carry
Address Bus
25. The ability of a capacitor to store electrical charge.
Acceptor
Choke
ASCII
Capacitance
26. An expression of variables and operators used to express the operation of a logic circuit
Boolean expression
Compiler
Associative law
DIMM
27. A electrical property of matter that exist because of an excess or a deficiency of electrons. Can be either positive or negative
AND
Control Bus
ASCII
Charge
28. The process of converting an analog signal to digital form
Choke
DMA
Commutative Law
Analog- to- digital (A/D) conversion
29. The beginning address of a segment of memory
Assembly language
Thevenin Equivalent Circuit
Base address
Bus arbitration
30. An energy source that uses a chemical reaction to convert chemical energy into electrical energy.
Battery
Branch Current
Dynamic Memory
Bias
31. A type of PLD nonvolatile programmable link that can be left open or can be shorted once as directed by the program
Analog- to- digital (A/D) conversion
ABEL(Advance Boolean Expression Language)
Antifuse
Base
32. A filter that passes a range of frequencies lying between two critical freqencies and rejects frequencies above and below that range.
Acceptor
Band- pass filter
Capacity
ANSI
33. American Standard Code for Information Interchange; the most widely used alphanumeric code.
Capacity
Asynchronous counter
ASCII
Decode
34. In a pulse waveform - the height or maximum value of the pulse as measured from its low level.
Charge- coupled device
Boundary scan
Amplitude
Counter
35. A software compiler language for SPLD programming; a type of hardware description language (HDL)
Address Bus
Distributive Law
ABEL(Advance Boolean Expression Language)
Aliasing
36. In a PLD - a matrix formed by rows of product- term lines columns of input lines with a programmable cell at each junctions. In VHDL - an array is an ordered set of individual items called elements with a single identifier name.
Array
Battery
Compiler
DMA
37. A document that specifies parameter values and operating conditions for an integrated circuits or other device
Data Sheet
Baseline
Controller
DCE
38. Information in numeric - alphabetic - or other form.
ASCII
Design flow
Data
Buffer
39. A reduction of the output signal compared to the input signal - resulting in a ratio with a value of less than 1 for the output voltage to the input voltage of a circuit.
Adjacency
Attenuation
Balanced Load
Clear
40. A stage of the DSP pipeline operation in which instructions are assigned to functional units and are decoded.
Adder
Decode
Dual in - line package
Baseline
41. The process that prevents two sources from using a bus at the same time
Decrement
Atomic number
AND
Bus arbitration
42. A digital code in which each of the decimal digits - 0 through 9 - is represented by a group of four bits
Binary
bed- of- nails
Binary coded decimal
Commutative Law
43. In Boolean algebra - the OR operation
Kirchoff's Current Law(KCL)
DIMM
Comparator
Boolean addition
44. A VHDL feature that can be used to predefine the logic function for multiple use throughout a program or programs
Bit
Component
ALU
CMOS Complementary Metal Oxide Semiconductor
45. An arrangement of electrical and/or electronic components interconnected in such a way as to perform a specified function
Astable
Circuit
Center Tap
CMOS Complementary Metal Oxide Semiconductor
46. The unit of electrical current
Ampere
Address Bus
Acceptor
Analog- to- digital (A/D) conversion
47. An electrical instrument used to measure current
CLB (Configurable Logic Block)
Aliasing
Ammeter
D Flip-Flop
48. Having two values or states; describes a number system that has a base of two and utilizes 1 and 0 as its digits
Binary
Control Unit
D Flip-Flop
Bode Plot
49. A bridge circuit that is in the balanced state as indicated by 0 V across the output.
Balanced Bridge
Bus
Kirchoff's Current Law(KCL)
Apparent power
50. A complex programmable logic device that consists basically of muliple SPLD arrays with programmable interconnections.
CPLD
Band- pass filter
AHDL
Bistable