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Test your basic knowledge |
Digital Fundamentals
Start Test
Study First
Subject
:
engineering
Instructions:
Answer 50 questions in 15 minutes.
If you are not ready to take this test, you can
study here
.
Match each statement with the correct term.
Don't refresh. All questions and answers are randomly picked and ordered every time you load a test.
This is a study tool. The 3 wrong answers for each question are randomly chosen from answers to other questions. So, you might find at times the answers obvious, but you will see it re-enforces your understanding as you take the test each time.
1. A method for the automated testing of printed circuit boards in which the board is mounted on a fixture that resembles a bed of nails that makes contact with test points
bed- of- nails
BEDO DRAM
DTE
Access time
2. The normal level of a pulse waveform; the voltage level in the absence of a pulse.
Admittance
Data bus
Baseline
ALU
3. The action of a circuit in which it accepts current into its output from a load
Vx=(Vs * Rx) /RT
Baseline
Current sinking
Ampere- hour(Ah) rating
4. A type of IC package whose leads must pass through holes to the other side of a PC board
Dual in - line package
Bus
Carry generation
Dynamic Memory
5. A document that specifies parameter values and operating conditions for an integrated circuits or other device
Delta Modulation
DAT
Data Sheet
Decode
6. A reduction of the output signal compared to the input signal - resulting in a ratio with a value of less than 1 for the output voltage to the input voltage of a circuit.
Buffer
Attenuation
Design flow
Bus interface unit
7. American wire gauge; a standardization based on wire diameter
Dividend
AWG
Demultiplexer
Diode
8. Having two opposites charge carriers within the transistor structure
Bipolar
Vx=(Vs * Rx) /RT
Assembler
Astable
9. A code within DOS that allows various operations on files and includes a primitive assembler; to eliminate a problem in hardware or software.
BEDO DRAM
Debug
Decrement
AND gate
10. Sum of all currents entering a node is equal to the sum of all currents leaving the same node
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11. The VHDL unit that describes the internal operation of a logic function; the internal functional arrangement of the elements that give a device its particular operating characteristics.
Carry
ALU
Address Bus
Architecture
12. A stage of the DSP pipeline operation in which instructions are assigned to functional units and are decoded.
Access time
Circuit
Cache memory
Decode
13. Characteristic of cells in a Karnaugh map in which there is a single- variable change from one cell to another cell next to it on any of its four sides
Code
Clock
BEDO DRAM
Adjacency
14. A class of integrated logic circuits that is implemented with a type of field effect transistor
ANSI
Duty cycle
Attenuation
CMOS Complementary Metal Oxide Semiconductor
15. A method for internally testing a PLD based on the JTAG standard (IEEE std.)
Assembly language
Boundary scan
Central processing unit
Controller
16. The effect created when a signal is sampled at less than twice the signal frequency. Aliasing creates unwanted frequencies that interfere with the signal frequency.
Component
Aliasing
AWG
Debug
17. The process or sequence of operations carried out to program a target device
Analog- to- digital (A/D) conversion
Demultiplexer
Design flow
Associative law
18. A circuit (digital service) that switches digital data from one input line to several output lines in a specified time sequence
Demultiplexer
Admittance
Assembly language
Carry
19. A complex programmable logic device that consists basically of muliple SPLD arrays with programmable interconnections.
CPLD
Branch
TTL
Amplitude
20. A circuit with a complete current path
Circuit
Closed circuit
Debug
AHDL
21. An asynchronous input used to reset a flip- flop (make the Q output 0); to place a register or counter in the state in which it contains all 0's
CLB (Configurable Logic Block)
Clear
Kirchoff's Voltage Law
Current sinking
22. Characterized by ten states or values
Decade
Boundary scan
Cache memory
Norton's Theorem
23. Basic input/output system; a set of programs in ROM that interfaces the I/) devices in a computer system
Commutative Law
BIOS
Carry propagation
Ampere
24. A unit of the cross - sectional area of a wire.
Balanced Load
Assembly language
Circular Mil (CM)
Bandwidth
25. The time from the application of a valid memory address to the appearance of valid output data
Base address
ABEL(Advance Boolean Expression Language)
DSP
Access time
26. In a pulse waveform - the height or maximum value of the pulse as measured from its low level.
Amplitude
DSP
Carry
Commutative Law
27. Transistor-Transistor Logic and is implemented with bipolar junction transistors
Delta Modulation
Boolean algebra
TTL
Ammeter
28. Dual in - line memory module
Battery
DIMM
Bus arbitration
Analog- to- digital (A/D) conversion
29. The law that states ORing several variables and then ANDing the single variable with each of the several variables and the ORing the product
Distributive Law
Kirchoff's Voltage Law
Balanced Load
Band- stop filter
30. A condition where all the load currents are equal and the neutral current is zero
Dual in - line package
Attenuation
Balanced Load
DRAM
31. A theorem that states that any amount of voltage sources and current sources can be combined into a single current source with a parallel resistor.
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32. Arithmetic Logic Unit; the key processing element of a microprocessor that perfoms arithmetic and logic operations.
Bistable
ALU
Capacitor
Design flow
33. Burst extended data output dynamic random- access memory
Cache memory
BEDO DRAM
Bit
Band- pass filter
34. A resettable protective device used for interrupting execessive current in an electric circuit
Base address
Carry generation
Base
Circuit Breaker
35. A circuit that prevents loading of an input or output
Decade Counter
Buffer
Controller
Capacitance
36. Digital Signal Processor; a special type of microprocessor that processes data in real time
DSP
BEDO DRAM
Bandwidth
Clock
37. A relatively small - high- speed memory that stores the most recently used instructions or data from the larger but slower main memory
Cache memory
Complement
Alphanumeric
Decade
38. Dynamic random- access memory; a type of semiconductor memory that uses capacitors as the storage elements and is a volatile - read/write memory
DRAM
Circuit
BJT
Capacitance
39. A programming language that uses English like words and has a one- to- one correspondence to machine language
Choke
Bipolar
Clear
Assembly language
40. Voltage Divider Rule in determining TEC Thevenin Equivalence Circuit
Vx=(Vs * Rx) /RT
CMOS
Dividend
Controller
41. The digit generated when the sum of two binary digits exceeds 1
Thevenin Equivalent Circuit
Antifuse
Carry
Bit time
42. Bipolar junction transistor; a semiconductor device used for switching or amplification. A BJT has two junctions - the base- emitter junction and the base- collector junction
DMA
Decade Counter
Duty cycle
BJT
43. A series of bits describing a final design that is sent to the target device during programming
ASCII
Bias
ABEL(Advance Boolean Expression Language)
Bitstream
44. The process of producing an output carry in full- adder when both input bits are 1s.
Amplitude
Boundary scan
Analog- to- digital (A/D) conversion
Carry generation
45. The portion of the CPU that interfaces with the system buses and fetches instructions - reads operands - and writes results.
Bus interface unit
Bandwidth
Average value
DCE
46. A logic gate that produces a High output only when all of the inputs are HIGH
Ammeter
Data Sheet
Charge
AND gate
47. A nominally continuous electrical signal that varies in amplitude or frequency in response to changes in sound - light - heat - position - or pressure.
Analog
Base
Counter
CLB (Configurable Logic Block)
48. An arrangement of electrical and/or electronic components interconnected in such a way as to perform a specified function
Bipolar
Adjacency
Circuit
Angular Velocity
49. A type of inductor used to block or choke off high frequencies
Carry generation
Dual in - line package
Choke
Decoder
50. A program that converts English- like mnemonics into machine code
Adjacency
Complement
Norton's Theorem
Assembler