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Test your basic knowledge |
Digital Fundamentals
Start Test
Study First
Subject
:
engineering
Instructions:
Answer 50 questions in 15 minutes.
If you are not ready to take this test, you can
study here
.
Match each statement with the correct term.
Don't refresh. All questions and answers are randomly picked and ordered every time you load a test.
This is a study tool. The 3 wrong answers for each question are randomly chosen from answers to other questions. So, you might find at times the answers obvious, but you will see it re-enforces your understanding as you take the test each time.
1. A series of bits describing a final design that is sent to the target device during programming
DIMM
Diode
Bitstream
Bipolar
2. A number given in ampere- hours determined by multiplying the current times the length of the time (h) a battery can deliver that current to a load
Delta Modulation
Ampere- hour(Ah) rating
Kirchoff's Voltage Law
Current sinking
3. A two terminal circuit containing voltage sources - current sources - and resistors can be modeled as a voltage source in series with a resistor
BJT
Don't Care...
Binary
Thevenin Equivalent Circuit
4. A digital code in which each of the decimal digits - 0 through 9 - is represented by a group of four bits
Compiler
Astable
Debug
Binary coded decimal
5. The beginning address of a segment of memory
Boolean multiplication
Carry
Base address
Analog- to- digital (A/D) conversion
6. Burst extended data output dynamic random- access memory
Bias
BEDO DRAM
Bandwidth
Boolean multiplication
7. The average of a sine wave over one half- cycle. It is 0.637 times the peak value.
Capacitance Reactance
Decoder
CPLD
Average value
8. The normal level of a pulse waveform; the voltage level in the absence of a pulse.
Complement
Carry propagation
Baseline
Duty cycle
9. A electrical property of matter that exist because of an excess or a deficiency of electrons. Can be either positive or negative
Acceptor
Charge
Bandwidth
Norton's Theorem
10. A digital circuit device that converts coded information into another (familiar) or noncoded form
Admittance
Decoder
Data Sheet
Charge- coupled device
11. A bidirectional set of conductive paths on which data or instruction codes are transferred into a microprocessor or on which the result of an operation is sent out from the microprocessor
Balanced Load
Data bus
Capacitor
Angular Velocity
12. In a pulse waveform - the height or maximum value of the pulse as measured from its low level.
Decimal
Amplitude
Duty cycle
AWG
13. Describes a number system with a base of ten
Decimal
DTE
bed- of- nails
Don't Care...
14. An asynchronous input used to reset a flip- flop (make the Q output 0); to place a register or counter in the state in which it contains all 0's
Analog
Clear
Demultiplexer
bed- of- nails
15. An array of AND gates consisting of a matrix of programmable interconnection
Analog- to- digital converter(ADC)
Astable
Addend
AND array
16. A combination of logic gates interconnected to produce a specified Boolean function with no storage or memory capability; sometimes called combinatorial logic
CLB (Configurable Logic Block)
Combinational logic
Band- pass filter
Control Unit
17. The process that prevents two sources from using a bus at the same time
Bus arbitration
Code
Capacitor
Buffer
18. The location of a given storage cell or group of cells in a memory; a unique memory location containing on byte
Data Selector
Address
Apparent power
CMOS Complementary Metal Oxide Semiconductor
19. A type of IC package whose leads must pass through holes to the other side of a PC board
Circuit
Center Tap
Dual in - line package
Code
20. In addition (Oring) and multiplication (ANDing) of three or more variables - the order in which the variables are grouped makes no difference
Adder
Band- pass filter
Associative law
Array
21. The time from the application of a valid memory address to the appearance of valid output data
Thevenin Equivalent Circuit
Access time
Analog
AND
22. A method for internally testing a PLD based on the JTAG standard (IEEE std.)
Kirchoff's Current Law(KCL)
BIOS
Access time
Boundary scan
23. An instrument that can specify each of the other instruments on the bus as either a talker or a listener for the purpose of data transfer.
Controller
Bitstream
Astable
AWG
24. A method for the automated testing of printed circuit boards in which the board is mounted on a fixture that resembles a bed of nails that makes contact with test points
bed- of- nails
DMA
Concurrency
AND gate
25. A type of inductor used to block or choke off high frequencies
Choke
Clear
Ammeter
Alphanumeric
26. The ability of a capacitor to store electrical charge.
Counter
Capacitance
Bleeder Current
Charge
27. A relatively small - high- speed memory that stores the most recently used instructions or data from the larger but slower main memory
Cache memory
DMA
Cross - assembler
DRAM
28. A circuit (digital service) that switches digital data from one input line to several output lines in a specified time sequence
Band- stop filter
AND array
Demultiplexer
Circuit
29. Stands for Complementary Metal-Oxide Semiconductor and is implemented with a type of field transistor
Circuit Breaker
BJT
Astable
CMOS
30. A document that specifies parameter values and operating conditions for an integrated circuits or other device
Address Bus
Combinational logic
Charge
Data Sheet
31. The smallest particle of an element possessing the unique characteristics of that element.
DRAM
Atom
Center Tap
Commutative Law
32. Data Terminal equipment
Norton's Theorem
DTE
Ammeter
Binary
33. The portion within the microprocessor that provides the timing and control signals for getting data into and out of the microprocessor and for synchronizing the execution of instructions.
Control Unit
Circuit
DAT
DRAM
34. The phasor combination of resistive power (true power) and reactive power. The unit is the volt- amperes (VA).
Data
Binary coded decimal
Acceptor
Apparent power
35. An electrical device consisting of two conductive plates separated by an insulating material and possessing the property of capacitance.
Clear
Thevenin Equivalent Circuit
BJT
Capacitor
36. Sum of all the voltage drops in series equals to the source voltage
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37. The application of a dc voltage to an electronic device to produce a desired mode of operation
Closed circuit
Compiler
Addend
Bias
38. A VHDL feature that can be used to predefine the logic function for multiple use throughout a program or programs
Digital linear tape
Code
Component
Address
39. A condition where all the load currents are equal and the neutral current is zero
Architecture
CPLD
Balanced Load
Astable
40. A device used to convert an analog signal to a sequence of digital codes
Vx=(Vs * Rx) /RT
Circuit
Analog- to- digital converter(ADC)
Bus interface unit
41. A filter that rejects a range of frequencies lying between two critical frequencies and passes frequencies above and below that range.
Band- stop filter
Band- pass filter
Duty cycle
Antifuse
42. A bridge circuit that is in the balanced state as indicated by 0 V across the output.
Bus interface unit
Balanced Load
Data bus
Balanced Bridge
43. A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmable interconnect that is used to connect logic modules within the CLB
TTL
CLB (Configurable Logic Block)
Kirchoff's Voltage Law
ALU
44. The process of converting an analog signal to digital form
Concurrency
DRAM
Comparator
Analog- to- digital (A/D) conversion
45. The rotational rate of a phasor which is related to the frequency of the sine wave that the phasor represents
Bistable
Buffer
Angular Velocity
DMA
46. The process of producing an output carry in full- adder when both input bits are 1s.
Adder
Carry generation
Atomic number
Alphanumeric
47. The total number of data units(bits - nibbles - bytes - words) that a memory can store.
Debug
Buffer
Capacity
Dual in - line package
48. Digital audio tape; a type of magnetic tape format
Byte
Branch
Design flow
DAT
49. The law that states ORing several variables and then ANDing the single variable with each of the several variables and the ORing the product
Distributive Law
Choke
Kirchoff's Voltage Law
Thevenin Equivalent Circuit
50. A type of semiconductor memory having capacitive storage cells that lose stored data over a period of time and therefore must be refreshed.
AND gate
Dynamic Memory
bed- of- nails
ASCII
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