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Test your basic knowledge |
Digital Fundamentals
Start Test
Study First
Subject
:
engineering
Instructions:
Answer 50 questions in 15 minutes.
If you are not ready to take this test, you can
study here
.
Match each statement with the correct term.
Don't refresh. All questions and answers are randomly picked and ordered every time you load a test.
This is a study tool. The 3 wrong answers for each question are randomly chosen from answers to other questions. So, you might find at times the answers obvious, but you will see it re-enforces your understanding as you take the test each time.
1. In addition (Oring) and multiplication (ANDing) of three or more variables - the order in which the variables are grouped makes no difference
Associative law
Address
Concurrency
ANSI
2. The effect created when a signal is sampled at less than twice the signal frequency. Aliasing creates unwanted frequencies that interfere with the signal frequency.
Aliasing
Addend
Capacity
Debug
3. In addition - the number to which the addend is added
ASCII
Combinational logic
Augend
Bit time
4. The ratio of pulse width to period expressed as a percentage
bed- of- nails
Carry propagation
DMA
Duty cycle
5. A type of IC package whose leads must pass through holes to the other side of a PC board
Design flow
Capacitance Reactance
Dual in - line package
bed- of- nails
6. A programming language that uses English like words and has a one- to- one correspondence to machine language
Assembly language
Circuit
Cross - assembler
Bus
7. A interconnection of electrical components designed to produce a desired result. A basic circuits consists of a source - a load and an interconnecting current path.
Apparent power
Circuit
Alphanumeric
Carry generation
8. An expression of variables and operators used to express the operation of a logic circuit
Cross - assembler
AHDL
DAT
Boolean expression
9. A software compiler language for SPLD programming; a type of hardware description language (HDL)
Decade Counter
Data Sheet
DAT
ABEL(Advance Boolean Expression Language)
10. Dual in - line memory module
Adder
Atom
DIMM
Combinational logic
11. The total number of data units(bits - nibbles - bytes - words) that a memory can store.
Boolean algebra
Baseline
Dual in - line package
Capacity
12. In relation to VHDL feature that permits operations to be processed in a parallel;that is operations that occur simultaneously
Augend
AHDL
Concurrency
Bus contention
13. American wire gauge; a standardization based on wire diameter
Diode
AWG
Analog
Attenuation
14. A set of interconnections that interface one or more devices based on a standardized specification
ABEL(Advance Boolean Expression Language)
Decode
Binary coded decimal
Bus
15. The inverse of opposite of a number - in Boolean algebra - the inverse function - expressed with a bar over the variable. The complement of a 1 is a 0 - and vice versa
Complement
ALU
Bus
Decimal
16. A method for the automated testing of printed circuit boards in which the board is mounted on a fixture that resembles a bed of nails that makes contact with test points
Bidirectional shift Register
Demultiplexer
bed- of- nails
Bitstream
17. A theorem that states that any amount of voltage sources and current sources can be combined into a single current source with a parallel resistor.
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18. An energy source that uses a chemical reaction to convert chemical energy into electrical energy.
Kirchoff's Voltage Law
Charge
Dependency notation
Battery
19. Having two values or states; describes a number system that has a base of two and utilizes 1 and 0 as its digits
Dynamic Memory
CLB (Configurable Logic Block)
Binary
Collector
20. Characterized by ten states or values
Decade
CMOS
Don't Care...
TTL
21. A type of PLD nonvolatile programmable link that can be left open or can be shorted once as directed by the program
Bus
Commutative Law
Antifuse
AND
22. The portion of the CPU that interfaces with the system buses and fetches instructions - reads operands - and writes results.
DCE
Bus interface unit
Addend
Commutative Law
23. A document that specifies parameter values and operating conditions for an integrated circuits or other device
Access time
Bus contention
Buffer
Data Sheet
24. In a division operation the quantity that is being divided
Dividend
Combinational logic
AND array
DAT
25. The digit generated when the sum of two binary digits exceeds 1
Assembly language
Address
AND gate
Carry
26. A digital code in which each of the decimal digits - 0 through 9 - is represented by a group of four bits
Bus
Architecture
Binary coded decimal
Delta Modulation
27. In a PLD - a matrix formed by rows of product- term lines columns of input lines with a programmable cell at each junctions. In VHDL - an array is an ordered set of individual items called elements with a single identifier name.
Bistable
Array
ASCII
DRAM
28. A type of magnetic tape format
DSP
Central processing unit
Analog- to- digital (A/D) conversion
Digital linear tape
29. Arithmetic Logic Unit; the key processing element of a microprocessor that perfoms arithmetic and logic operations.
Asynchronous counter
Cache memory
Balanced Load
ALU
30. Stands for Complementary Metal-Oxide Semiconductor and is implemented with a type of field transistor
Alphanumeric
Commutative Law
Charge
CMOS
31. A circuit (digital service) that switches digital data from one input line to several output lines in a specified time sequence
Demultiplexer
Binary
Binary coded decimal
Debug
32. A filter that rejects a range of frequencies lying between two critical frequencies and passes frequencies above and below that range.
Branch
Band- stop filter
Carry generation
Binary
33. A filter that passes a range of frequencies lying between two critical freqencies and rejects frequencies above and below that range.
Charge- coupled device
Capacitance
Band- pass filter
Dual in - line package
34. The average of a sine wave over one half- cycle. It is 0.637 times the peak value.
Delta Modulation
Data Sheet
Access time
Average value
35. Data Communications equipment
Adjacency
DCE
Cache memory
Array
36. A measure of the ability of a reactive circuit to permit current; the reciprocal of impedance. the unit is the siemens
Debug
AND
Associative law
Admittance
37. A method of analog- to- digital conversion using a 1- bit quantization process
Byte
bed- of- nails
Delta Modulation
Distributive Law
38. An instrument that can specify each of the other instruments on the bus as either a talker or a listener for the purpose of data transfer.
Controller
Atom
Assembler
Address Bus
39. An asynchronous input used to reset a flip- flop (make the Q output 0); to place a register or counter in the state in which it contains all 0's
CMOS
BJT
Clear
Cache memory
40. A method for internally testing a PLD based on the JTAG standard (IEEE std.)
Buffer
BIOS
Boundary scan
Balanced Load
41. The normal level of a pulse waveform; the voltage level in the absence of a pulse.
Addend
Address Bus
Baseline
Clock
42. A condition where all the load currents are equal and the neutral current is zero
Balanced Load
Branch
DMA
ASCII
43. A VHDL feature that can be used to predefine the logic function for multiple use throughout a program or programs
Debug
Comparator
Component
BIOS
44. Having two directions. the stored data can be shifted right or left
Distributive Law
Charge- coupled device
Bidirectional shift Register
Branch
45. The number of protons in a nucleus
Array
Distributive Law
CLB (Configurable Logic Block)
Atomic number
46. A binary digit - which can be either 1 or 0
Bit
Branch Current
Cascade
Base address
47. An arrangement of electrical and/or electronic components interconnected in such a way as to perform a specified function
Dynamic Memory
Circuit
Thevenin Equivalent Circuit
Adjacency
48. A transformer in which the primary and secondary are in a single winding
Boolean expression
Bus arbitration
Bit
Autotransformer
49. A combination of input literals that cannot occur and can be used as a 1 or 0 on a Karnaugh Map for simplification
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50. Sum of all currents entering a node is equal to the sum of all currents leaving the same node
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