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Digital Fundamentals
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Study First
Subject
:
engineering
Instructions:
Answer 50 questions in 15 minutes.
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study here
.
Match each statement with the correct term.
Don't refresh. All questions and answers are randomly picked and ordered every time you load a test.
This is a study tool. The 3 wrong answers for each question are randomly chosen from answers to other questions. So, you might find at times the answers obvious, but you will see it re-enforces your understanding as you take the test each time.
1. A receiving device on a bus
ASCII
Admittance
Acceptor
Counter
2. In Boolean algebra - the OR operation
Ammeter
Boolean multiplication
Concurrency
Boolean addition
3. The time from the application of a valid memory address to the appearance of valid output data
Access time
Ammeter
Baseline
Data
4. A stage of the DSP pipeline operation in which instructions are assigned to functional units and are decoded.
AND array
Carry
AWG
Decode
5. In addition - the number that is added to another number called the augend
Choke
BJT
Cascade
Addend
6. Information in numeric - alphabetic - or other form.
Associative law
Duty cycle
Battery
Data
7. A circuit that selects data from several inputs one at a time in a sequence and places them on the output; also called a multiplexer.
D Flip-Flop
Data Selector
DTE
Component
8. Altera HDL; a nonstandard HDL
AWG
Cross - assembler
AHDL
Base
9. A circuit with a complete current path
Collector
CPLD
Closed circuit
Analog
10. A one- way group of conductors from the to a memory - or other external device - on which the address code is sent
Bidirectional shift Register
Antifuse
DRAM
Address Bus
11. The law that states ORing several variables and then ANDing the single variable with each of the several variables and the ORing the product
Balanced Bridge
Atomic number
Distributive Law
Aliasing
12. A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmable interconnect that is used to connect logic modules within the CLB
CLB (Configurable Logic Block)
Code
CPLD
DTE
13. Dynamic random- access memory; a type of semiconductor memory that uses capacitors as the storage elements and is a volatile - read/write memory
Dependency notation
DRAM
Baseline
Commutative Law
14. An adverse condition that could occur if two or more devices try to communicate at the same time on a bus
Bus contention
Cache memory
Boundary scan
AWG
15. A set of conductive paths hat connects the CPU to other parts of the computer to coordinate its operations and to communicate with external devices
Control Bus
Decade
Bus arbitration
ASCII
16. In addition - the number to which the addend is added
Center Tap
Augend
Current sinking
Asynchronous counter
17. American National Standards Institute
Data Selector
Controller
ANSI
Binary
18. A program that converts English- like mnemonics into machine code
Code
Duty cycle
Assembler
ALU
19. A digital circuit capable of counting electronic events - such as pulses - by progressing through a sequence of binary states.
Counter
AND gate
ASCII
Duty cycle
20. The process or sequence of operations carried out to program a target device
DAT
Assembler
Design flow
Cache memory
21. The normal level of a pulse waveform; the voltage level in the absence of a pulse.
Bode Plot
AND gate
Baseline
Circuit Breaker
22. A type of inductor used to block or choke off high frequencies
Decade Counter
CMOS Complementary Metal Oxide Semiconductor
Choke
BIOS
23. A logic circuit used to add two binary numbers
Bit time
CMOS Complementary Metal Oxide Semiconductor
Adder
Control Unit
24. The graph of a filter's frequency response showing the change in the output voltage to input voltage ratio expressed in dB as a function of frequency for a constant input voltage
CLB (Configurable Logic Block)
Bode Plot
Address
Adjacency
25. One of the three regions in a bipolar Junction transistor(North junction of NpN)
Design flow
Closed circuit
Control Bus
Collector
26. A type of counter in which each stage is clocked from the output of the preceding stage.
Bus
Asynchronous counter
Balanced Bridge
Dynamic Memory
27. A combination of logic gates interconnected to produce a specified Boolean function with no storage or memory capability; sometimes called combinatorial logic
Combinational logic
Dual in - line package
AND array
Control Unit
28. A nominally continuous electrical signal that varies in amplitude or frequency in response to changes in sound - light - heat - position - or pressure.
Analog
Autotransformer
DAT
AHDL
29. A type of semiconductor memory having capacitive storage cells that lose stored data over a period of time and therefore must be refreshed.
Component
D Flip-Flop
Boundary scan
Dynamic Memory
30. The actual current in a branch
Circuit Breaker
Branch Current
Bipolar
AND
31. A series of bits describing a final design that is sent to the target device during programming
Battery
Bitstream
Addend
Capacitance Reactance
32. The process of converting an analog signal to digital form
Decade Counter
ABEL(Advance Boolean Expression Language)
Analog- to- digital (A/D) conversion
Bus contention
33. The interval of time occupied by a single bit in a sequence of bits; the period of the clock
Bit time
Branch
Cascade
Architecture
34. Dual in - line memory module
Binary coded decimal
Boolean addition
DIMM
ABEL(Advance Boolean Expression Language)
35. A filter that rejects a range of frequencies lying between two critical frequencies and passes frequencies above and below that range.
Base address
Antifuse
Acceptor
Band- stop filter
36. An application program in development software packages that controls the design flow process and translates source code into object code in a format that can be logically tested or downloaded to a target device
Thevenin Equivalent Circuit
Compiler
Capacity
Branch Current
37. A bidirectional set of conductive paths on which data or instruction codes are transferred into a microprocessor or on which the result of an operation is sent out from the microprocessor
Band- pass filter
Counter
Alphanumeric
Data bus
38. In a pulse waveform - the height or maximum value of the pulse as measured from its low level.
Band- stop filter
Asynchronous counter
Amplitude
Compiler
39. An instrument that can specify each of the other instruments on the bus as either a talker or a listener for the purpose of data transfer.
Controller
Cache memory
Address Bus
Control Unit
40. The digit generated when the sum of two binary digits exceeds 1
Decode
Kirchoff's Current Law(KCL)
Norton's Theorem
Carry
41. A method of analog- to- digital conversion using a 1- bit quantization process
Array
Delta Modulation
Decrement
Duty cycle
42. An array of AND gates consisting of a matrix of programmable interconnection
ANSI
AND array
CMOS
DRAM
43. The ability of a capacitor to store electrical charge.
Capacitance
BIOS
ANSI
Capacity
44. A binary digit - which can be either 1 or 0
Bit
Dividend
Bit time
Admittance
45. The VHDL unit that describes the internal operation of a logic function; the internal functional arrangement of the elements that give a device its particular operating characteristics.
Average value
Architecture
Data Selector
Bias
46. American Standard Code for Information Interchange; the most widely used alphanumeric code.
ASCII
Bus
Bus contention
AHDL
47. The total number of data units(bits - nibbles - bytes - words) that a memory can store.
Baseline
Boolean algebra
Buffer
Capacity
48. A VHDL feature that can be used to predefine the logic function for multiple use throughout a program or programs
Assembly language
Component
Control Bus
AWG
49. To connect 'end- to- end' as when several counters are connected from the terminal count output of one counter to the enable input of the next counter
Bandwidth
Adjacency
Cascade
Carry generation
50. A connection at the midpoint of a winding in a transformer
Data bus
Decoder
Bus contention
Center Tap
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