SUBJECTS
|
BROWSE
|
CAREER CENTER
|
POPULAR
|
JOIN
|
LOGIN
Business Skills
|
Soft Skills
|
Basic Literacy
|
Certifications
About
|
Help
|
Privacy
|
Terms
|
Email
Search
Test your basic knowledge |
Digital Fundamentals
Start Test
Study First
Subject
:
engineering
Instructions:
Answer 50 questions in 15 minutes.
If you are not ready to take this test, you can
study here
.
Match each statement with the correct term.
Don't refresh. All questions and answers are randomly picked and ordered every time you load a test.
This is a study tool. The 3 wrong answers for each question are randomly chosen from answers to other questions. So, you might find at times the answers obvious, but you will see it re-enforces your understanding as you take the test each time.
1. Altera HDL; a nonstandard HDL
Center Tap
Charge- coupled device
AHDL
ALU
2. The inverse of opposite of a number - in Boolean algebra - the inverse function - expressed with a bar over the variable. The complement of a 1 is a 0 - and vice versa
Clear
Carry
Complement
Code
3. A type of semiconductor memory having capacitive storage cells that lose stored data over a period of time and therefore must be refreshed.
Array
DRAM
Dynamic Memory
Bus
4. The current left after the total load current is subtracted from the total current into the circuit
Controller
Bleeder Current
Cross - assembler
Circuit
5. An electrical instrument used to measure current
Acceptor
Circular Mil (CM)
Ammeter
Data Selector
6. Sum of all currents entering a node is equal to the sum of all currents leaving the same node
Warning
: Invalid argument supplied for foreach() in
/var/www/html/basicversity.com/show_quiz.php
on line
183
7. A unit of the cross - sectional area of a wire.
Bias
Collector
Circular Mil (CM)
Bitstream
8. In a PLD - a matrix formed by rows of product- term lines columns of input lines with a programmable cell at each junctions. In VHDL - an array is an ordered set of individual items called elements with a single identifier name.
Battery
Data Selector
Augend
Array
9. An expression of variables and operators used to express the operation of a logic circuit
Carry propagation
BJT
Boolean expression
Buffer
10. In addition - the number to which the addend is added
Distributive Law
Augend
Bus contention
Data Selector
11. The interval of time occupied by a single bit in a sequence of bits; the period of the clock
Bit time
Data bus
Bus
CMOS
12. The normal level of a pulse waveform; the voltage level in the absence of a pulse.
Base
Aliasing
Baseline
Amplitude
13. A semiconductor device that conducts current in only one direction
Ammeter
Diode
Circuit Breaker
Decade Counter
14. The beginning address of a segment of memory
Base address
Aliasing
BIOS
Data bus
15. Transistor-Transistor Logic and is implemented with bipolar junction transistors
AWG
Address Bus
TTL
Dividend
16. A filter that rejects a range of frequencies lying between two critical frequencies and passes frequencies above and below that range.
Cross - assembler
Band- stop filter
AND array
Duty cycle
17. A logic circuit used to add two binary numbers
Bus
Control Bus
Adder
Boolean addition
18. A type of semiconductor memory that stores data in the form of charge packets and is serially accessed
Charge- coupled device
Associative law
Kirchoff's Voltage Law
Address Bus
19. The rotational rate of a phasor which is related to the frequency of the sine wave that the phasor represents
Assembler
Control Bus
Ampere- hour(Ah) rating
Angular Velocity
20. In addition (ORing) and multiplication (ANDing) of two variables the order in which the variables are ORed or ANDed makes no difference
Data
Address Bus
Commutative Law
Kirchoff's Voltage Law
21. A stage of the DSP pipeline operation in which instructions are assigned to functional units and are decoded.
Branch
Decode
Base address
Assembler
22. American National Standards Institute
Bistable
ANSI
DCE
Kirchoff's Current Law(KCL)
23. Having no stable state. An astable multivibrator oscillates between two quasi- stable states.
Astable
Bus
Architecture
BIOS
24. The opposition of a capacitor to permit current; the reciprocal of capacitive reactance. The unit is the siemens.
Capacitance Reactance
Delta Modulation
Bit time
Atomic number
25. A program that converts English- like mnemonics into machine code
Array
Assembler
Alphanumeric
Decade Counter
26. Dynamic random- access memory; a type of semiconductor memory that uses capacitors as the storage elements and is a volatile - read/write memory
Control Unit
Bidirectional shift Register
DRAM
Bipolar
27. Having two directions. the stored data can be shifted right or left
Bidirectional shift Register
CLB (Configurable Logic Block)
Boolean multiplication
ABEL(Advance Boolean Expression Language)
28. A interconnection of electrical components designed to produce a desired result. A basic circuits consists of a source - a load and an interconnecting current path.
Complement
Counter
Circuit
Associative law
29. A type of bistable multivibrator in which the output assumes the state of the D input on the triggering edge of a clock pulse.
TTL
Bus contention
D Flip-Flop
AWG
30. The VHDL unit that describes the internal operation of a logic function; the internal functional arrangement of the elements that give a device its particular operating characteristics.
CLB (Configurable Logic Block)
Architecture
DRAM
Battery
31. In a division operation the quantity that is being divided
Ampere
Digital linear tape
Access time
Dividend
32. A measure of the ability of a reactive circuit to permit current; the reciprocal of impedance. the unit is the siemens
Boundary scan
Code
DTE
Admittance
33. Consisting of numerals - letters - and other characters
AND array
Carry generation
Alphanumeric
Vx=(Vs * Rx) /RT
34. Arithmetic Logic Unit; the key processing element of a microprocessor that perfoms arithmetic and logic operations.
DSP
ALU
Data bus
Decimal
35. Stands for Complementary Metal-Oxide Semiconductor and is implemented with a type of field transistor
Bistable
CMOS
Debug
Cascade
36. A method of analog- to- digital conversion using a 1- bit quantization process
DTE
Delta Modulation
AND
Design flow
37. Dual in - line memory module
Cache memory
DSP
DIMM
D Flip-Flop
38. A method for internally testing a PLD based on the JTAG standard (IEEE std.)
Branch Current
Boundary scan
Byte
Bidirectional shift Register
39. The ratio of pulse width to period expressed as a percentage
Balanced Bridge
BJT
Buffer
Duty cycle
40. To connect 'end- to- end' as when several counters are connected from the terminal count output of one counter to the enable input of the next counter
Atom
Ampere
DRAM
Cascade
41. The process of converting an analog signal to digital form
Dynamic Memory
Analog- to- digital (A/D) conversion
Antifuse
Capacitance
42. The process of producing an output carry in full- adder when both input bits are 1s.
Astable
Debug
AWG
Carry generation
43. A bidirectional set of conductive paths on which data or instruction codes are transferred into a microprocessor or on which the result of an operation is sent out from the microprocessor
Capacitance Reactance
Data bus
Design flow
Decode
44. A combination of input literals that cannot occur and can be used as a 1 or 0 on a Karnaugh Map for simplification
Warning
: Invalid argument supplied for foreach() in
/var/www/html/basicversity.com/show_quiz.php
on line
183
45. A group of eight bits
CMOS Complementary Metal Oxide Semiconductor
Byte
Average value
DSP
46. In Boolean algebra - the AND operation
Decrement
Boolean multiplication
Baseline
Architecture
47. A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmable interconnect that is used to connect logic modules within the CLB
Vx=(Vs * Rx) /RT
CLB (Configurable Logic Block)
Don't Care...
Boolean multiplication
48. A one- way group of conductors from the to a memory - or other external device - on which the address code is sent
Band- pass filter
Address Bus
Dividend
Alphanumeric
49. An asynchronous input used to reset a flip- flop (make the Q output 0); to place a register or counter in the state in which it contains all 0's
Branch Current
Cache memory
Clear
Bus contention
50. A type of PLD nonvolatile programmable link that can be left open or can be shorted once as directed by the program
Acceptor
Address
Antifuse
Code