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Test your basic knowledge |
Digital Fundamentals
Start Test
Study First
Subject
:
engineering
Instructions:
Answer 50 questions in 15 minutes.
If you are not ready to take this test, you can
study here
.
Match each statement with the correct term.
Don't refresh. All questions and answers are randomly picked and ordered every time you load a test.
This is a study tool. The 3 wrong answers for each question are randomly chosen from answers to other questions. So, you might find at times the answers obvious, but you will see it re-enforces your understanding as you take the test each time.
1. The portion within the microprocessor that provides the timing and control signals for getting data into and out of the microprocessor and for synchronizing the execution of instructions.
Bus interface unit
Access time
Analog
Control Unit
2. The effect created when a signal is sampled at less than twice the signal frequency. Aliasing creates unwanted frequencies that interfere with the signal frequency.
AHDL
Analog
Aliasing
Bus
3. To connect 'end- to- end' as when several counters are connected from the terminal count output of one counter to the enable input of the next counter
Circuit Breaker
Cascade
Ammeter
Alphanumeric
4. In a PLD - a matrix formed by rows of product- term lines columns of input lines with a programmable cell at each junctions. In VHDL - an array is an ordered set of individual items called elements with a single identifier name.
Circuit
Array
Comparator
Augend
5. A bidirectional set of conductive paths on which data or instruction codes are transferred into a microprocessor or on which the result of an operation is sent out from the microprocessor
Data bus
Debug
Balanced Bridge
Carry propagation
6. A theorem that states that any amount of voltage sources and current sources can be combined into a single current source with a parallel resistor.
7. A circuit that prevents loading of an input or output
Complement
Buffer
Alphanumeric
Cascade
8. The interval of time occupied by a single bit in a sequence of bits; the period of the clock
Carry generation
Alphanumeric
Bit time
Analog- to- digital converter(ADC)
9. A group of eight bits
Access time
Astable
Byte
Address Bus
10. An energy source that uses a chemical reaction to convert chemical energy into electrical energy.
Battery
Capacitance
ANSI
Design flow
11. A method for internally testing a PLD based on the JTAG standard (IEEE std.)
Capacitance
Boundary scan
Autotransformer
Byte
12. A logic gate that produces a High output only when all of the inputs are HIGH
AND gate
Address Bus
Angular Velocity
Assembler
13. A basic logic operation in which a true(high) output occurs only when all the input conditions are true (high)
Capacity
Boolean expression
CMOS
AND
14. The time from the application of a valid memory address to the appearance of valid output data
Clear
Access time
Assembly language
Control Unit
15. A VHDL feature that can be used to predefine the logic function for multiple use throughout a program or programs
Component
Autotransformer
Dual in - line package
Decrement
16. Altera HDL; a nonstandard HDL
AHDL
AWG
Address
AND gate
17. The average of a sine wave over one half- cycle. It is 0.637 times the peak value.
bed- of- nails
Average value
CMOS Complementary Metal Oxide Semiconductor
DSP
18. In addition (ORing) and multiplication (ANDing) of two variables the order in which the variables are ORed or ANDed makes no difference
Amplitude
Dual in - line package
Commutative Law
Balanced Load
19. The phasor combination of resistive power (true power) and reactive power. The unit is the volt- amperes (VA).
Decimal
Debug
Analog- to- digital converter(ADC)
Apparent power
20. A filter that passes a range of frequencies lying between two critical freqencies and rejects frequencies above and below that range.
Band- pass filter
Decode
Data Sheet
Bidirectional shift Register
21. A complex programmable logic device that consists basically of muliple SPLD arrays with programmable interconnections.
CPLD
Bus contention
Astable
Amplitude
22. Characterized by ten states or values
Binary coded decimal
Diode
Decade
Adder
23. A filter that rejects a range of frequencies lying between two critical frequencies and passes frequencies above and below that range.
Ammeter
Band- stop filter
CMOS Complementary Metal Oxide Semiconductor
Assembler
24. The action of a circuit in which it accepts current into its output from a load
Cross - assembler
Analog
Current sinking
AND
25. A one- way group of conductors from the to a memory - or other external device - on which the address code is sent
Address Bus
Concurrency
Control Bus
ALU
26. A measure of the ability of a reactive circuit to permit current; the reciprocal of impedance. the unit is the siemens
Center Tap
AND gate
Admittance
Bandwidth
27. In Boolean algebra - the OR operation
Boolean addition
DRAM
Bleeder Current
Band- pass filter
28. A type of semiconductor memory that stores data in the form of charge packets and is serially accessed
Charge- coupled device
Norton's Theorem
TTL
Compiler
29. A series of bits describing a final design that is sent to the target device during programming
Choke
Bitstream
Debug
Bidirectional shift Register
30. A transformer in which the primary and secondary are in a single winding
Bipolar
Bus contention
Autotransformer
AND array
31. The ability of a capacitor to store electrical charge.
Capacitance
Baseline
Norton's Theorem
Array
32. The VHDL unit that describes the internal operation of a logic function; the internal functional arrangement of the elements that give a device its particular operating characteristics.
Decade
Architecture
Antifuse
Bipolar
33. A electrical property of matter that exist because of an excess or a deficiency of electrons. Can be either positive or negative
Bus contention
Aliasing
Charge
Design flow
34. The total number of data units(bits - nibbles - bytes - words) that a memory can store.
Bias
Capacity
Circuit
Counter
35. The beginning address of a segment of memory
Carry propagation
Data bus
Base address
Bus interface unit
36. A logic circuit used to add two binary numbers
Buffer
Adder
Circuit
Clock
37. A circuit (digital service) that switches digital data from one input line to several output lines in a specified time sequence
Demultiplexer
DIMM
Ammeter
Asynchronous counter
38. An electrical instrument used to measure current
Boolean multiplication
Cascade
Ammeter
Decade
39. Burst extended data output dynamic random- access memory
Bipolar
BEDO DRAM
Astable
Acceptor
40. A relatively small - high- speed memory that stores the most recently used instructions or data from the larger but slower main memory
AND gate
Clear
Control Bus
Cache memory
41. A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmable interconnect that is used to connect logic modules within the CLB
Circuit
Clock
Vx=(Vs * Rx) /RT
CLB (Configurable Logic Block)
42. A receiving device on a bus
AND
BIOS
Band- stop filter
Acceptor
43. Describes a number system with a base of ten
Decimal
Dual in - line package
Array
bed- of- nails
44. An adverse condition that could occur if two or more devices try to communicate at the same time on a bus
ALU
Circular Mil (CM)
Data bus
Bus contention
45. A type of IC package whose leads must pass through holes to the other side of a PC board
ANSI
DRAM
AND array
Dual in - line package
46. A binary digit - which can be either 1 or 0
Bus
Bit
Bleeder Current
CMOS Complementary Metal Oxide Semiconductor
47. A two terminal circuit containing voltage sources - current sources - and resistors can be modeled as a voltage source in series with a resistor
ASCII
Thevenin Equivalent Circuit
Cascade
Don't Care...
48. A type of counter in which each stage is clocked from the output of the preceding stage.
Bus interface unit
BEDO DRAM
Asynchronous counter
Admittance
49. The process of producing an output carry in full- adder when both input bits are 1s.
Kirchoff's Current Law(KCL)
Carry generation
Compiler
Circuit
50. The range of frequencies for which the current (or output voltage) is equal to or greater than 70.7% of its value at the resonant frequency that is considered to be passed by a filter.
Capacity
Bandwidth
Boundary scan
Clock