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Test your basic knowledge |
Digital Fundamentals
Start Test
Study First
Subject
:
engineering
Instructions:
Answer 50 questions in 15 minutes.
If you are not ready to take this test, you can
study here
.
Match each statement with the correct term.
Don't refresh. All questions and answers are randomly picked and ordered every time you load a test.
This is a study tool. The 3 wrong answers for each question are randomly chosen from answers to other questions. So, you might find at times the answers obvious, but you will see it re-enforces your understanding as you take the test each time.
1. The graph of a filter's frequency response showing the change in the output voltage to input voltage ratio expressed in dB as a function of frequency for a constant input voltage
Bit time
Decrement
Bode Plot
Clear
2. The inverse of opposite of a number - in Boolean algebra - the inverse function - expressed with a bar over the variable. The complement of a 1 is a 0 - and vice versa
Atom
Carry propagation
Branch Current
Complement
3. A reduction of the output signal compared to the input signal - resulting in a ratio with a value of less than 1 for the output voltage to the input voltage of a circuit.
Architecture
Attenuation
Control Unit
Component
4. The phasor combination of resistive power (true power) and reactive power. The unit is the volt- amperes (VA).
Capacitance
Apparent power
Decade
Decode
5. The process of converting an analog signal to digital form
Concurrency
Balanced Load
Autotransformer
Analog- to- digital (A/D) conversion
6. A type of semiconductor memory having capacitive storage cells that lose stored data over a period of time and therefore must be refreshed.
Acceptor
Dynamic Memory
Atomic number
Asynchronous counter
7. Dynamic random- access memory; a type of semiconductor memory that uses capacitors as the storage elements and is a volatile - read/write memory
Kirchoff's Current Law(KCL)
CPLD
CMOS Complementary Metal Oxide Semiconductor
DRAM
8. Having two values or states; describes a number system that has a base of two and utilizes 1 and 0 as its digits
Byte
Addend
Binary
Architecture
9. Information in numeric - alphabetic - or other form.
Data
DMA
Byte
Collector
10. The effect created when a signal is sampled at less than twice the signal frequency. Aliasing creates unwanted frequencies that interfere with the signal frequency.
Decode
Aliasing
CMOS
Bistable
11. A digital circuit capable of counting electronic events - such as pulses - by progressing through a sequence of binary states.
Combinational logic
Byte
Counter
ABEL(Advance Boolean Expression Language)
12. A complex programmable logic device that consists basically of muliple SPLD arrays with programmable interconnections.
CPLD
Boolean algebra
Architecture
Bus
13. A class of integrated logic circuits that is implemented with a type of field effect transistor
Closed circuit
CMOS Complementary Metal Oxide Semiconductor
DSP
Attenuation
14. A electrical property of matter that exist because of an excess or a deficiency of electrons. Can be either positive or negative
Kirchoff's Voltage Law
Concurrency
CPLD
Charge
15. The number of protons in a nucleus
Bias
Bitstream
Atomic number
Antifuse
16. In a PLD - a matrix formed by rows of product- term lines columns of input lines with a programmable cell at each junctions. In VHDL - an array is an ordered set of individual items called elements with a single identifier name.
Array
Alphanumeric
Balanced Bridge
Autotransformer
17. Having two opposites charge carriers within the transistor structure
Analog- to- digital (A/D) conversion
Clear
Bipolar
Data
18. A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmable interconnect that is used to connect logic modules within the CLB
Balanced Load
CLB (Configurable Logic Block)
Branch
Atomic number
19. A stage of the DSP pipeline operation in which instructions are assigned to functional units and are decoded.
Bus contention
Augend
Acceptor
Decode
20. Having two stable states. Flip- flops and latches are bistable multivibrators.
Cross - assembler
Bidirectional shift Register
Capacitance
Bistable
21. A filter that rejects a range of frequencies lying between two critical frequencies and passes frequencies above and below that range.
Complement
Boolean addition
Band- stop filter
Balanced Load
22. The main part of a computer responsible for control and processing of data; the core of a DSP that processes the program instructions
Dependency notation
Central processing unit
Code
Boolean algebra
23. A circuit with a complete current path
Analog- to- digital converter(ADC)
Commutative Law
Closed circuit
BEDO DRAM
24. The process of producing an output carry in full- adder when both input bits are 1s.
Carry generation
Carry
Access time
Kirchoff's Current Law(KCL)
25. Dual in - line memory module
Associative law
DIMM
Aliasing
AND
26. An asynchronous input used to reset a flip- flop (make the Q output 0); to place a register or counter in the state in which it contains all 0's
Atom
DAT
Clear
Balanced Load
27. An application program in development software packages that controls the design flow process and translates source code into object code in a format that can be logically tested or downloaded to a target device
Commutative Law
Asynchronous counter
Compiler
Baseline
28. Burst extended data output dynamic random- access memory
BEDO DRAM
Code
Admittance
Battery
29. Voltage Divider Rule in determining TEC Thevenin Equivalence Circuit
Ampere
DCE
Vx=(Vs * Rx) /RT
DAT
30. A document that specifies parameter values and operating conditions for an integrated circuits or other device
Data Sheet
Cascade
Branch Current
Boolean algebra
31. A type of IC package whose leads must pass through holes to the other side of a PC board
Dual in - line package
AND
Dependency notation
Architecture
32. The beginning address of a segment of memory
Decrement
Base address
Branch
Capacitance
33. A type of counter in which each stage is clocked from the output of the preceding stage.
Asynchronous counter
Boolean multiplication
Branch
BEDO DRAM
34. In addition (ORing) and multiplication (ANDing) of two variables the order in which the variables are ORed or ANDed makes no difference
Norton's Theorem
Counter
Circuit
Commutative Law
35. In relation to VHDL feature that permits operations to be processed in a parallel;that is operations that occur simultaneously
Combinational logic
Assembly language
Bit time
Concurrency
36. A digital circuit device that converts coded information into another (familiar) or noncoded form
DAT
Decoder
Assembler
Analog- to- digital converter(ADC)
37. A circuit (digital service) that switches digital data from one input line to several output lines in a specified time sequence
Atomic number
Norton's Theorem
Demultiplexer
Autotransformer
38. To connect 'end- to- end' as when several counters are connected from the terminal count output of one counter to the enable input of the next counter
Bandwidth
CPLD
Bus
Cascade
39. Data Communications equipment
Concurrency
DCE
BIOS
Adjacency
40. A method for the automated testing of printed circuit boards in which the board is mounted on a fixture that resembles a bed of nails that makes contact with test points
bed- of- nails
Analog- to- digital converter(ADC)
Bus interface unit
Dependency notation
41. A condition where all the load currents are equal and the neutral current is zero
BEDO DRAM
Boolean addition
Carry propagation
Balanced Load
42. An expression of variables and operators used to express the operation of a logic circuit
DRAM
Boolean expression
Clear
Carry propagation
43. An array of AND gates consisting of a matrix of programmable interconnection
Binary
Dynamic Memory
Ampere
AND array
44. The VHDL unit that describes the internal operation of a logic function; the internal functional arrangement of the elements that give a device its particular operating characteristics.
Architecture
Adder
Digital linear tape
Norton's Theorem
45. The digit generated when the sum of two binary digits exceeds 1
Ammeter
AWG
Decade
Carry
46. Digital Signal Processor; a special type of microprocessor that processes data in real time
DSP
Decrement
DAT
Duty cycle
47. The process or sequence of operations carried out to program a target device
Amplitude
Data bus
Design flow
Closed circuit
48. A relatively small - high- speed memory that stores the most recently used instructions or data from the larger but slower main memory
DCE
Cache memory
Carry
Band- pass filter
49. A binary digit - which can be either 1 or 0
Bit time
Clear
Bit
Atom
50. American wire gauge; a standardization based on wire diameter
AWG
Adjacency
Bandwidth
Closed circuit
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