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Test your basic knowledge |
Digital Fundamentals
Start Test
Study First
Subject
:
engineering
Instructions:
Answer 50 questions in 15 minutes.
If you are not ready to take this test, you can
study here
.
Match each statement with the correct term.
Don't refresh. All questions and answers are randomly picked and ordered every time you load a test.
This is a study tool. The 3 wrong answers for each question are randomly chosen from answers to other questions. So, you might find at times the answers obvious, but you will see it re-enforces your understanding as you take the test each time.
1. A stage of the DSP pipeline operation in which instructions are assigned to functional units and are decoded.
Decode
Amplitude
Compiler
Assembly language
2. An application program in development software packages that controls the design flow process and translates source code into object code in a format that can be logically tested or downloaded to a target device
Compiler
Bitstream
Bleeder Current
Cascade
3. A reduction of the output signal compared to the input signal - resulting in a ratio with a value of less than 1 for the output voltage to the input voltage of a circuit.
Diode
Attenuation
Closed circuit
Cross - assembler
4. The normal level of a pulse waveform; the voltage level in the absence of a pulse.
Choke
Baseline
BJT
Bit
5. A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmable interconnect that is used to connect logic modules within the CLB
Bit
ASCII
CLB (Configurable Logic Block)
Address Bus
6. Dual in - line memory module
Dual in - line package
Dependency notation
DIMM
Boolean expression
7. Basic input/output system; a set of programs in ROM that interfaces the I/) devices in a computer system
BIOS
Control Unit
Bus arbitration
Bipolar
8. A VHDL feature that can be used to predefine the logic function for multiple use throughout a program or programs
Component
Boolean expression
Circuit
Closed circuit
9. The interval of time occupied by a single bit in a sequence of bits; the period of the clock
AND gate
Bus contention
AND array
Bit time
10. A transformer in which the primary and secondary are in a single winding
Autotransformer
Center Tap
Carry
Adder
11. A resettable protective device used for interrupting execessive current in an electric circuit
DTE
Circuit Breaker
Charge
DCE
12. An electrical device consisting of two conductive plates separated by an insulating material and possessing the property of capacitance.
Capacitor
Decode
Code
Bus arbitration
13. A binary digit - which can be either 1 or 0
Bit
AND array
Code
Dynamic Memory
14. Describes a number system with a base of ten
DSP
Data Selector
Decimal
Delta Modulation
15. A number given in ampere- hours determined by multiplying the current times the length of the time (h) a battery can deliver that current to a load
Counter
Ampere- hour(Ah) rating
Addend
Byte
16. The rotational rate of a phasor which is related to the frequency of the sine wave that the phasor represents
Charge
Angular Velocity
Data Sheet
ALU
17. The main part of a computer responsible for control and processing of data; the core of a DSP that processes the program instructions
Don't Care...
Code
Central processing unit
CMOS
18. Sum of all currents entering a node is equal to the sum of all currents leaving the same node
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on line
183
19. A condition where all the load currents are equal and the neutral current is zero
Balanced Load
Battery
Baseline
Branch
20. The actual current in a branch
Branch Current
Analog- to- digital (A/D) conversion
DCE
Average value
21. The mathematics of logic circuits
Bias
Bleeder Current
Kirchoff's Current Law(KCL)
Boolean algebra
22. A one- way group of conductors from the to a memory - or other external device - on which the address code is sent
Bipolar
Bus
Address Bus
Band- pass filter
23. American National Standards Institute
Branch Current
ANSI
CMOS
Binary
24. A software compiler language for SPLD programming; a type of hardware description language (HDL)
ABEL(Advance Boolean Expression Language)
Data Selector
Balanced Load
DSP
25. Altera HDL; a nonstandard HDL
Assembler
CMOS Complementary Metal Oxide Semiconductor
Dynamic Memory
AHDL
26. The action of a circuit in which it accepts current into its output from a load
Balanced Load
Bit
Current sinking
Dividend
27. The effect created when a signal is sampled at less than twice the signal frequency. Aliasing creates unwanted frequencies that interfere with the signal frequency.
Aliasing
Decode
Bode Plot
Atom
28. To decrease the binary state of a counter by one
Branch Current
Decrement
CMOS Complementary Metal Oxide Semiconductor
Ampere
29. An array of AND gates consisting of a matrix of programmable interconnection
Central processing unit
Dividend
AND array
Bus
30. A group of eight bits
Antifuse
Closed circuit
BEDO DRAM
Byte
31. A method of analog- to- digital conversion using a 1- bit quantization process
Ammeter
Array
Average value
Delta Modulation
32. In addition (Oring) and multiplication (ANDing) of three or more variables - the order in which the variables are grouped makes no difference
Closed circuit
Carry propagation
Associative law
Balanced Load
33. The law that states ORing several variables and then ANDing the single variable with each of the several variables and the ORing the product
Distributive Law
DRAM
DCE
Clear
34. The unit of electrical current
Dual in - line package
Acceptor
Balanced Load
Ampere
35. A nominally continuous electrical signal that varies in amplitude or frequency in response to changes in sound - light - heat - position - or pressure.
Counter
Cross - assembler
Base address
Analog
36. A two terminal circuit containing voltage sources - current sources - and resistors can be modeled as a voltage source in series with a resistor
Thevenin Equivalent Circuit
Capacitor
Debug
Ammeter
37. A combined coder and decoder
Code
Duty cycle
CPLD
Address
38. The basic timing signal in a digital system; a periodic waveform in which the interval between pulses equals the time for one bit; the triggering input of a flip- flop
BIOS
Cascade
Clock
Dependency notation
39. The process that prevents two sources from using a bus at the same time
Code
DTE
Apparent power
Bus arbitration
40. The current left after the total load current is subtracted from the total current into the circuit
Bias
Duty cycle
Bleeder Current
DIMM
41. To connect 'end- to- end' as when several counters are connected from the terminal count output of one counter to the enable input of the next counter
Apparent power
Complement
Attenuation
Cascade
42. One of the three regions in a bipolar Junction transistor(North junction of NpN)
Boolean multiplication
Collector
Carry
Adjacency
43. A type of bistable multivibrator in which the output assumes the state of the D input on the triggering edge of a clock pulse.
Decade
Charge
Concurrency
D Flip-Flop
44. Direct memory access; a method to directly interface a peripheral device to memory without using the CPU for control
BJT
Adder
DMA
DRAM
45. A type of inductor used to block or choke off high frequencies
Choke
Capacitance Reactance
Bistable
bed- of- nails
46. A bridge circuit that is in the balanced state as indicated by 0 V across the output.
Balanced Bridge
Vx=(Vs * Rx) /RT
Bus interface unit
Atomic number
47. A circuit with a complete current path
Average value
Ammeter
Addend
Closed circuit
48. An arrangement of electrical and/or electronic components interconnected in such a way as to perform a specified function
ASCII
Choke
Circuit
Center Tap
49. A measure of the ability of a reactive circuit to permit current; the reciprocal of impedance. the unit is the siemens
Band- stop filter
Admittance
Access time
Cache memory
50. The average of a sine wave over one half- cycle. It is 0.637 times the peak value.
Circuit
Average value
Kirchoff's Current Law(KCL)
AND array