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Test your basic knowledge |
Digital Fundamentals
Start Test
Study First
Subject
:
engineering
Instructions:
Answer 50 questions in 15 minutes.
If you are not ready to take this test, you can
study here
.
Match each statement with the correct term.
Don't refresh. All questions and answers are randomly picked and ordered every time you load a test.
This is a study tool. The 3 wrong answers for each question are randomly chosen from answers to other questions. So, you might find at times the answers obvious, but you will see it re-enforces your understanding as you take the test each time.
1. The process of producing an output carry in full- adder when both input bits are 1s.
Data Sheet
Bode Plot
Carry generation
DCE
2. In addition - the number that is added to another number called the augend
Addend
Clear
DAT
AND gate
3. The application of a dc voltage to an electronic device to produce a desired mode of operation
Data bus
Bias
Dynamic Memory
Circuit Breaker
4. An arrangement of electrical and/or electronic components interconnected in such a way as to perform a specified function
Design flow
Decoder
Circuit
CMOS Complementary Metal Oxide Semiconductor
5. A receiving device on a bus
Duty cycle
Demultiplexer
Acceptor
ANSI
6. In a division operation the quantity that is being divided
Bandwidth
Dividend
Ampere
Battery
7. The average of a sine wave over one half- cycle. It is 0.637 times the peak value.
Counter
Buffer
Average value
DTE
8. The basic timing signal in a digital system; a periodic waveform in which the interval between pulses equals the time for one bit; the triggering input of a flip- flop
Analog
Clock
Circuit Breaker
Base
9. A unit of the cross - sectional area of a wire.
Ampere- hour(Ah) rating
Decimal
Circular Mil (CM)
Compiler
10. A method of analog- to- digital conversion using a 1- bit quantization process
Bistable
Kirchoff's Voltage Law
Delta Modulation
Ammeter
11. The beginning address of a segment of memory
Bode Plot
Boolean algebra
Base address
Buffer
12. A condition where all the load currents are equal and the neutral current is zero
Bode Plot
Baseline
Commutative Law
Balanced Load
13. A VHDL feature that can be used to predefine the logic function for multiple use throughout a program or programs
Battery
Component
Boolean addition
Acceptor
14. Having no stable state. An astable multivibrator oscillates between two quasi- stable states.
Astable
CLB (Configurable Logic Block)
Acceptor
Charge- coupled device
15. American Standard Code for Information Interchange; the most widely used alphanumeric code.
CLB (Configurable Logic Block)
ASCII
Amplitude
Bus contention
16. A filter that passes a range of frequencies lying between two critical freqencies and rejects frequencies above and below that range.
Component
Duty cycle
Band- pass filter
AWG
17. A stage of the DSP pipeline operation in which instructions are assigned to functional units and are decoded.
Adder
Decode
Bode Plot
Dividend
18. A digital circuit capable of counting electronic events - such as pulses - by progressing through a sequence of binary states.
Current sinking
Counter
Bit time
ANSI
19. In addition (ORing) and multiplication (ANDing) of two variables the order in which the variables are ORed or ANDed makes no difference
Branch
Collector
Address
Commutative Law
20. A transformer in which the primary and secondary are in a single winding
Autotransformer
Commutative Law
Boolean algebra
Addend
21. The ratio of pulse width to period expressed as a percentage
Charge
DCE
Cache memory
Duty cycle
22. An array of AND gates consisting of a matrix of programmable interconnection
Clear
Balanced Load
Kirchoff's Current Law(KCL)
AND array
23. The rotational rate of a phasor which is related to the frequency of the sine wave that the phasor represents
Bus arbitration
Binary coded decimal
Angular Velocity
Bandwidth
24. A bridge circuit that is in the balanced state as indicated by 0 V across the output.
BEDO DRAM
Balanced Bridge
Array
Central processing unit
25. Information in numeric - alphabetic - or other form.
Balanced Load
Bus contention
Capacity
Data
26. The interval of time occupied by a single bit in a sequence of bits; the period of the clock
Bit time
Closed circuit
Bus contention
DIMM
27. A digital code in which each of the decimal digits - 0 through 9 - is represented by a group of four bits
Atom
Binary coded decimal
Astable
Analog
28. A type of PLD nonvolatile programmable link that can be left open or can be shorted once as directed by the program
Antifuse
Carry generation
DAT
Component
29. A group of eight bits
Byte
Battery
Data
DRAM
30. An asynchronous input used to reset a flip- flop (make the Q output 0); to place a register or counter in the state in which it contains all 0's
Bus arbitration
Analog- to- digital converter(ADC)
AND gate
Clear
31. A programming language that uses English like words and has a one- to- one correspondence to machine language
Assembly language
Boolean algebra
Antifuse
Average value
32. An application program in development software packages that controls the design flow process and translates source code into object code in a format that can be logically tested or downloaded to a target device
Compiler
Data bus
Assembler
Access time
33. Stands for Complementary Metal-Oxide Semiconductor and is implemented with a type of field transistor
Atom
CMOS
CMOS Complementary Metal Oxide Semiconductor
DIMM
34. A circuit that prevents loading of an input or output
Decade
Boundary scan
Buffer
Don't Care...
35. A type of inductor used to block or choke off high frequencies
Capacity
Thevenin Equivalent Circuit
Choke
Adjacency
36. The main part of a computer responsible for control and processing of data; the core of a DSP that processes the program instructions
Decade
Center Tap
Choke
Central processing unit
37. Basic input/output system; a set of programs in ROM that interfaces the I/) devices in a computer system
Decrement
BIOS
CPLD
Distributive Law
38. The time from the application of a valid memory address to the appearance of valid output data
Augend
Boolean addition
Access time
Duty cycle
39. A resettable protective device used for interrupting execessive current in an electric circuit
Vx=(Vs * Rx) /RT
Circuit Breaker
Digital linear tape
Admittance
40. A type of semiconductor memory having capacitive storage cells that lose stored data over a period of time and therefore must be refreshed.
Alphanumeric
Dynamic Memory
AND gate
CMOS
41. A theorem that states that any amount of voltage sources and current sources can be combined into a single current source with a parallel resistor.
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42. A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmable interconnect that is used to connect logic modules within the CLB
Boundary scan
Dependency notation
Amplitude
CLB (Configurable Logic Block)
43. A filter that rejects a range of frequencies lying between two critical frequencies and passes frequencies above and below that range.
Bit time
Branch
Dividend
Band- stop filter
44. To connect 'end- to- end' as when several counters are connected from the terminal count output of one counter to the enable input of the next counter
Collector
DMA
Boolean multiplication
Cascade
45. The unit of electrical current
Architecture
Ampere
Bit
Carry
46. Having two opposites charge carriers within the transistor structure
Addend
Bipolar
Battery
AND
47. A combination of input literals that cannot occur and can be used as a 1 or 0 on a Karnaugh Map for simplification
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48. A set of interconnections that interface one or more devices based on a standardized specification
Choke
Bus
ANSI
Delta Modulation
49. The graph of a filter's frequency response showing the change in the output voltage to input voltage ratio expressed in dB as a function of frequency for a constant input voltage
Buffer
Apparent power
Combinational logic
Bode Plot
50. Characteristic of cells in a Karnaugh map in which there is a single- variable change from one cell to another cell next to it on any of its four sides
Kirchoff's Current Law(KCL)
Charge
Adjacency
Comparator