SUBJECTS
|
BROWSE
|
CAREER CENTER
|
POPULAR
|
JOIN
|
LOGIN
Business Skills
|
Soft Skills
|
Basic Literacy
|
Certifications
About
|
Help
|
Privacy
|
Terms
|
Email
Search
Test your basic knowledge |
Digital Fundamentals
Start Test
Study First
Subject
:
engineering
Instructions:
Answer 50 questions in 15 minutes.
If you are not ready to take this test, you can
study here
.
Match each statement with the correct term.
Don't refresh. All questions and answers are randomly picked and ordered every time you load a test.
This is a study tool. The 3 wrong answers for each question are randomly chosen from answers to other questions. So, you might find at times the answers obvious, but you will see it re-enforces your understanding as you take the test each time.
1. A type of semiconductor memory that stores data in the form of charge packets and is serially accessed
ABEL(Advance Boolean Expression Language)
CMOS Complementary Metal Oxide Semiconductor
Array
Charge- coupled device
2. Dynamic random- access memory; a type of semiconductor memory that uses capacitors as the storage elements and is a volatile - read/write memory
Data
DRAM
Don't Care...
Clear
3. A filter that passes a range of frequencies lying between two critical freqencies and rejects frequencies above and below that range.
Bus contention
CMOS
Ampere- hour(Ah) rating
Band- pass filter
4. The beginning address of a segment of memory
Base address
Branch Current
Kirchoff's Current Law(KCL)
Circuit Breaker
5. A number given in ampere- hours determined by multiplying the current times the length of the time (h) a battery can deliver that current to a load
Base
Balanced Load
Ampere- hour(Ah) rating
Bit
6. A class of integrated logic circuits that is implemented with a type of field effect transistor
Debug
Design flow
CMOS Complementary Metal Oxide Semiconductor
Thevenin Equivalent Circuit
7. An adverse condition that could occur if two or more devices try to communicate at the same time on a bus
Compiler
Charge
Bus contention
Atomic number
8. The number of protons in a nucleus
Design flow
Current sinking
Don't Care...
Atomic number
9. Stands for Complementary Metal-Oxide Semiconductor and is implemented with a type of field transistor
DMA
Decade
CMOS
Address Bus
10. A circuit that selects data from several inputs one at a time in a sequence and places them on the output; also called a multiplexer.
Bus contention
Choke
Data Selector
Boolean multiplication
11. Digital audio tape; a type of magnetic tape format
DAT
Charge
Kirchoff's Current Law(KCL)
Clear
12. A type of IC package whose leads must pass through holes to the other side of a PC board
AND gate
Dual in - line package
AWG
Collector
13. Burst extended data output dynamic random- access memory
Choke
BEDO DRAM
Delta Modulation
Base address
14. The action of a circuit in which it accepts current into its output from a load
Duty cycle
Average value
Apparent power
Current sinking
15. A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmable interconnect that is used to connect logic modules within the CLB
AND
Clock
CLB (Configurable Logic Block)
Capacitance
16. Information in numeric - alphabetic - or other form.
Acceptor
Data
Charge- coupled device
DMA
17. Describes a number system with a base of ten
Bleeder Current
Circular Mil (CM)
Bit time
Decimal
18. A notational system for logic symbols that specifies input and output relationships thus fully defining a given function
AHDL
Duty cycle
Dependency notation
Capacitance Reactance
19. A code within DOS that allows various operations on files and includes a primitive assembler; to eliminate a problem in hardware or software.
Augend
Bus contention
Cache memory
Debug
20. A filter that rejects a range of frequencies lying between two critical frequencies and passes frequencies above and below that range.
Capacity
Band- stop filter
Central processing unit
DRAM
21. American National Standards Institute
ANSI
Adjacency
AND
Center Tap
22. Data Terminal equipment
DTE
Compiler
Astable
Balanced Bridge
23. A binary digit - which can be either 1 or 0
DMA
Bit
Data bus
Concurrency
24. In addition (ORing) and multiplication (ANDing) of two variables the order in which the variables are ORed or ANDed makes no difference
Asynchronous counter
BJT
CMOS Complementary Metal Oxide Semiconductor
Commutative Law
25. In a pulse waveform - the height or maximum value of the pulse as measured from its low level.
Carry
Data Selector
Amplitude
Base address
26. A combination of input literals that cannot occur and can be used as a 1 or 0 on a Karnaugh Map for simplification
Warning
: Invalid argument supplied for foreach() in
/var/www/html/basicversity.com/show_quiz.php
on line
183
27. The process of producing an output carry in full- adder when both input bits are 1s.
Bias
Bus interface unit
Closed circuit
Carry generation
28. A theorem that states that any amount of voltage sources and current sources can be combined into a single current source with a parallel resistor.
Warning
: Invalid argument supplied for foreach() in
/var/www/html/basicversity.com/show_quiz.php
on line
183
29. A logic circuit used to add two binary numbers
Bus
Capacitance
Code
Adder
30. The VHDL unit that describes the internal operation of a logic function; the internal functional arrangement of the elements that give a device its particular operating characteristics.
Apparent power
Analog- to- digital (A/D) conversion
Carry generation
Architecture
31. In addition (Oring) and multiplication (ANDing) of three or more variables - the order in which the variables are grouped makes no difference
Boolean addition
Associative law
Base
Delta Modulation
32. A connection at the midpoint of a winding in a transformer
Decoder
Balanced Load
Center Tap
Address
33. A digital circuit capable of counting electronic events - such as pulses - by progressing through a sequence of binary states.
AND gate
Counter
Ampere- hour(Ah) rating
Average value
34. Consisting of numerals - letters - and other characters
Alphanumeric
Complement
Kirchoff's Voltage Law
Associative law
35. Voltage Divider Rule in determining TEC Thevenin Equivalence Circuit
Vx=(Vs * Rx) /RT
Access time
Analog- to- digital converter(ADC)
Bitstream
36. Altera HDL; a nonstandard HDL
ALU
Control Unit
AHDL
Bleeder Current
37. An application program in development software packages that controls the design flow process and translates source code into object code in a format that can be logically tested or downloaded to a target device
ANSI
Compiler
Address Bus
Clear
38. A interconnection of electrical components designed to produce a desired result. A basic circuits consists of a source - a load and an interconnecting current path.
Access time
Circuit
Diode
BIOS
39. A resettable protective device used for interrupting execessive current in an electric circuit
Circuit Breaker
Analog
DMA
AHDL
40. An expression of variables and operators used to express the operation of a logic circuit
Boolean expression
Compiler
Battery
Bandwidth
41. A digital code in which each of the decimal digits - 0 through 9 - is represented by a group of four bits
Binary coded decimal
Component
Bitstream
Binary
42. Direct memory access; a method to directly interface a peripheral device to memory without using the CPU for control
DMA
Array
DAT
TTL
43. The normal level of a pulse waveform; the voltage level in the absence of a pulse.
CLB (Configurable Logic Block)
Complement
Baseline
CPLD
44. The graph of a filter's frequency response showing the change in the output voltage to input voltage ratio expressed in dB as a function of frequency for a constant input voltage
Kirchoff's Current Law(KCL)
Capacitor
Capacitance
Bode Plot
45. A combination of logic gates interconnected to produce a specified Boolean function with no storage or memory capability; sometimes called combinatorial logic
Combinational logic
Diode
Analog- to- digital converter(ADC)
Addend
46. The time from the application of a valid memory address to the appearance of valid output data
Access time
Addend
BJT
Clear
47. A bidirectional set of conductive paths on which data or instruction codes are transferred into a microprocessor or on which the result of an operation is sent out from the microprocessor
Data bus
Controller
Boundary scan
Bipolar
48. A circuit (digital service) that switches digital data from one input line to several output lines in a specified time sequence
Boolean algebra
Demultiplexer
Distributive Law
ANSI
49. The process or sequence of operations carried out to program a target device
Design flow
Control Unit
Boolean addition
Cache memory
50. In a PLD - a matrix formed by rows of product- term lines columns of input lines with a programmable cell at each junctions. In VHDL - an array is an ordered set of individual items called elements with a single identifier name.
Bandwidth
Addend
Apparent power
Array