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Test your basic knowledge |
Digital Fundamentals
Start Test
Study First
Subject
:
engineering
Instructions:
Answer 50 questions in 15 minutes.
If you are not ready to take this test, you can
study here
.
Match each statement with the correct term.
Don't refresh. All questions and answers are randomly picked and ordered every time you load a test.
This is a study tool. The 3 wrong answers for each question are randomly chosen from answers to other questions. So, you might find at times the answers obvious, but you will see it re-enforces your understanding as you take the test each time.
1. A filter that rejects a range of frequencies lying between two critical frequencies and passes frequencies above and below that range.
Base address
Code
Band- stop filter
Circuit Breaker
2. The basic timing signal in a digital system; a periodic waveform in which the interval between pulses equals the time for one bit; the triggering input of a flip- flop
Circular Mil (CM)
CPLD
Clock
Boolean multiplication
3. A type of semiconductor memory that stores data in the form of charge packets and is serially accessed
Charge- coupled device
Adjacency
Delta Modulation
Control Bus
4. A filter that passes a range of frequencies lying between two critical freqencies and rejects frequencies above and below that range.
Architecture
Charge
Band- pass filter
Balanced Load
5. A set of interconnections that interface one or more devices based on a standardized specification
Dividend
Assembler
AND
Bus
6. An application program in development software packages that controls the design flow process and translates source code into object code in a format that can be logically tested or downloaded to a target device
DCE
Compiler
bed- of- nails
Center Tap
7. A method for internally testing a PLD based on the JTAG standard (IEEE std.)
Circuit Breaker
Balanced Load
Boundary scan
Binary coded decimal
8. A measure of the ability of a reactive circuit to permit current; the reciprocal of impedance. the unit is the siemens
Choke
Admittance
Bode Plot
Analog
9. The time from the application of a valid memory address to the appearance of valid output data
CPLD
Access time
Band- stop filter
Bus interface unit
10. A theorem that states that any amount of voltage sources and current sources can be combined into a single current source with a parallel resistor.
11. A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmable interconnect that is used to connect logic modules within the CLB
Cascade
DTE
Astable
CLB (Configurable Logic Block)
12. Having no stable state. An astable multivibrator oscillates between two quasi- stable states.
Astable
Boolean algebra
Circuit
Address Bus
13. An adverse condition that could occur if two or more devices try to communicate at the same time on a bus
Autotransformer
BJT
Bus contention
Dynamic Memory
14. A electrical property of matter that exist because of an excess or a deficiency of electrons. Can be either positive or negative
Base address
Band- stop filter
DMA
Charge
15. A combination of logic gates interconnected to produce a specified Boolean function with no storage or memory capability; sometimes called combinatorial logic
Combinational logic
Bistable
Associative law
Data Selector
16. A program that translates an assembly language program for one type of microprocessor to an assembly language for another type of microprocessor
Delta Modulation
Cross - assembler
Attenuation
Aliasing
17. American wire gauge; a standardization based on wire diameter
Clock
Center Tap
AWG
CMOS Complementary Metal Oxide Semiconductor
18. Bipolar junction transistor; a semiconductor device used for switching or amplification. A BJT has two junctions - the base- emitter junction and the base- collector junction
CMOS
BJT
ANSI
Bandwidth
19. A nominally continuous electrical signal that varies in amplitude or frequency in response to changes in sound - light - heat - position - or pressure.
Control Unit
Analog
Apparent power
Binary
20. Characteristic of cells in a Karnaugh map in which there is a single- variable change from one cell to another cell next to it on any of its four sides
AND
Digital linear tape
Adjacency
Don't Care...
21. Dual in - line memory module
DIMM
BEDO DRAM
Choke
DSP
22. In a PLD - a matrix formed by rows of product- term lines columns of input lines with a programmable cell at each junctions. In VHDL - an array is an ordered set of individual items called elements with a single identifier name.
Array
Center Tap
ALU
Decimal
23. A type of inductor used to block or choke off high frequencies
Bus interface unit
Current sinking
Band- stop filter
Choke
24. The process of converting an analog signal to digital form
BIOS
Ampere- hour(Ah) rating
Analog- to- digital (A/D) conversion
Vx=(Vs * Rx) /RT
25. An electrical instrument used to measure current
AWG
Antifuse
Ammeter
Branch Current
26. A digital code in which each of the decimal digits - 0 through 9 - is represented by a group of four bits
Clear
Binary coded decimal
Alphanumeric
Digital linear tape
27. In addition - the number to which the addend is added
Don't Care...
Augend
Circuit Breaker
Component
28. The VHDL unit that describes the internal operation of a logic function; the internal functional arrangement of the elements that give a device its particular operating characteristics.
Dependency notation
Data
Cross - assembler
Architecture
29. A digital circuit that compares the magnitudes of two quantiities and produces an output indicating the relationship of the quantities
Array
Comparator
Battery
BIOS
30. American Standard Code for Information Interchange; the most widely used alphanumeric code.
Aliasing
Component
Capacitor
ASCII
31. An expression of variables and operators used to express the operation of a logic circuit
Code
Ammeter
Boolean expression
TTL
32. A type of IC package whose leads must pass through holes to the other side of a PC board
Distributive Law
Code
Dual in - line package
Battery
33. Data Terminal equipment
DTE
Vx=(Vs * Rx) /RT
AHDL
Component
34. A method of analog- to- digital conversion using a 1- bit quantization process
Delta Modulation
CLB (Configurable Logic Block)
CMOS
Center Tap
35. A method for the automated testing of printed circuit boards in which the board is mounted on a fixture that resembles a bed of nails that makes contact with test points
bed- of- nails
Address
AND gate
Bistable
36. American National Standards Institute
BIOS
Component
AWG
ANSI
37. Digital audio tape; a type of magnetic tape format
Control Unit
DAT
Comparator
Dual in - line package
38. In addition (ORing) and multiplication (ANDing) of two variables the order in which the variables are ORed or ANDed makes no difference
Commutative Law
Analog
Kirchoff's Current Law(KCL)
Counter
39. Stands for Complementary Metal-Oxide Semiconductor and is implemented with a type of field transistor
Astable
Bus contention
Design flow
CMOS
40. The total number of data units(bits - nibbles - bytes - words) that a memory can store.
Data Selector
Associative law
Architecture
Capacity
41. Having two opposites charge carriers within the transistor structure
Commutative Law
Dependency notation
Associative law
Bipolar
42. The action of a circuit in which it accepts current into its output from a load
Balanced Bridge
DRAM
Assembly language
Current sinking
43. A semiconductor device that conducts current in only one direction
Cross - assembler
Component
Carry propagation
Diode
44. A reduction of the output signal compared to the input signal - resulting in a ratio with a value of less than 1 for the output voltage to the input voltage of a circuit.
AND
Central processing unit
Ampere
Attenuation
45. The effect created when a signal is sampled at less than twice the signal frequency. Aliasing creates unwanted frequencies that interfere with the signal frequency.
Attenuation
Assembler
Aliasing
Delta Modulation
46. The rotational rate of a phasor which is related to the frequency of the sine wave that the phasor represents
Counter
Debug
Angular Velocity
Clear
47. The application of a dc voltage to an electronic device to produce a desired mode of operation
DTE
Analog- to- digital (A/D) conversion
Counter
Bias
48. An array of AND gates consisting of a matrix of programmable interconnection
ABEL(Advance Boolean Expression Language)
AND array
Comparator
Control Bus
49. A condition where all the load currents are equal and the neutral current is zero
ALU
Complement
Balanced Load
Adjacency
50. A transformer in which the primary and secondary are in a single winding
Control Bus
Current sinking
Decode
Autotransformer