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Test your basic knowledge |
Digital Fundamentals
Start Test
Study First
Subject
:
engineering
Instructions:
Answer 50 questions in 15 minutes.
If you are not ready to take this test, you can
study here
.
Match each statement with the correct term.
Don't refresh. All questions and answers are randomly picked and ordered every time you load a test.
This is a study tool. The 3 wrong answers for each question are randomly chosen from answers to other questions. So, you might find at times the answers obvious, but you will see it re-enforces your understanding as you take the test each time.
1. To connect 'end- to- end' as when several counters are connected from the terminal count output of one counter to the enable input of the next counter
Buffer
Cascade
Balanced Load
Debug
2. The VHDL unit that describes the internal operation of a logic function; the internal functional arrangement of the elements that give a device its particular operating characteristics.
Branch Current
Architecture
Dividend
ANSI
3. In a pulse waveform - the height or maximum value of the pulse as measured from its low level.
Amplitude
Asynchronous counter
Bipolar
DRAM
4. A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmable interconnect that is used to connect logic modules within the CLB
Bias
CLB (Configurable Logic Block)
Addend
Bidirectional shift Register
5. Information in numeric - alphabetic - or other form.
Assembly language
Circuit Breaker
Data
Analog- to- digital (A/D) conversion
6. The ability of a capacitor to store electrical charge.
Angular Velocity
Controller
AND array
Capacitance
7. A logic gate that produces a High output only when all of the inputs are HIGH
DRAM
Adjacency
AND gate
Dynamic Memory
8. Arithmetic Logic Unit; the key processing element of a microprocessor that perfoms arithmetic and logic operations.
ALU
Bidirectional shift Register
BEDO DRAM
Comparator
9. A theorem that states that any amount of voltage sources and current sources can be combined into a single current source with a parallel resistor.
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10. In relation to VHDL feature that permits operations to be processed in a parallel;that is operations that occur simultaneously
Dual in - line package
Dependency notation
D Flip-Flop
Concurrency
11. Consisting of numerals - letters - and other characters
Alphanumeric
Boolean algebra
TTL
Bitstream
12. A digital circuit device that converts coded information into another (familiar) or noncoded form
Decoder
Address Bus
Choke
Charge- coupled device
13. The average of a sine wave over one half- cycle. It is 0.637 times the peak value.
Combinational logic
Code
Average value
Adder
14. The graph of a filter's frequency response showing the change in the output voltage to input voltage ratio expressed in dB as a function of frequency for a constant input voltage
Buffer
Bode Plot
CMOS
Bus interface unit
15. A programming language that uses English like words and has a one- to- one correspondence to machine language
Concurrency
Circuit
Assembly language
Capacitor
16. The process or sequence of operations carried out to program a target device
Bitstream
Addend
Assembly language
Design flow
17. A method of analog- to- digital conversion using a 1- bit quantization process
Capacitance
Analog
Base address
Delta Modulation
18. A VHDL feature that can be used to predefine the logic function for multiple use throughout a program or programs
Bus interface unit
Atomic number
Component
ANSI
19. A bidirectional set of conductive paths on which data or instruction codes are transferred into a microprocessor or on which the result of an operation is sent out from the microprocessor
Concurrency
Data bus
Ampere- hour(Ah) rating
Ammeter
20. A group of eight bits
Decade
Byte
Address
CLB (Configurable Logic Block)
21. An array of AND gates consisting of a matrix of programmable interconnection
Capacitance Reactance
DTE
AND array
CMOS
22. The opposition of a capacitor to permit current; the reciprocal of capacitive reactance. The unit is the siemens.
Cache memory
Capacitance Reactance
Closed circuit
Balanced Bridge
23. Sum of all currents entering a node is equal to the sum of all currents leaving the same node
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24. In addition (ORing) and multiplication (ANDing) of two variables the order in which the variables are ORed or ANDed makes no difference
Don't Care...
Branch
Dynamic Memory
Commutative Law
25. A relatively small - high- speed memory that stores the most recently used instructions or data from the larger but slower main memory
DMA
Cache memory
Vx=(Vs * Rx) /RT
Address Bus
26. The portion within the microprocessor that provides the timing and control signals for getting data into and out of the microprocessor and for synchronizing the execution of instructions.
Byte
Carry generation
Boolean algebra
Control Unit
27. A circuit with a complete current path
Vx=(Vs * Rx) /RT
Bleeder Current
Bandwidth
Closed circuit
28. Data Terminal equipment
Norton's Theorem
Charge
Average value
DTE
29. Having two values or states; describes a number system that has a base of two and utilizes 1 and 0 as its digits
Component
Analog- to- digital (A/D) conversion
Binary
BJT
30. A resettable protective device used for interrupting execessive current in an electric circuit
ASCII
Circuit Breaker
Array
Duty cycle
31. A type of bistable multivibrator in which the output assumes the state of the D input on the triggering edge of a clock pulse.
DIMM
DCE
Carry propagation
D Flip-Flop
32. The normal level of a pulse waveform; the voltage level in the absence of a pulse.
Baseline
Delta Modulation
Data
Dependency notation
33. In a division operation the quantity that is being divided
Bus
Dividend
Boolean multiplication
Attenuation
34. The basic timing signal in a digital system; a periodic waveform in which the interval between pulses equals the time for one bit; the triggering input of a flip- flop
Clock
Duty cycle
Circuit
Collector
35. A basic logic operation in which a true(high) output occurs only when all the input conditions are true (high)
Dual in - line package
CMOS Complementary Metal Oxide Semiconductor
Decade Counter
AND
36. Voltage Divider Rule in determining TEC Thevenin Equivalence Circuit
Binary
Vx=(Vs * Rx) /RT
Circular Mil (CM)
AHDL
37. A transformer in which the primary and secondary are in a single winding
Autotransformer
Addend
Analog
Data
38. A one- way group of conductors from the to a memory - or other external device - on which the address code is sent
DMA
Binary coded decimal
Address Bus
Digital linear tape
39. One of the three regions in a bipolar Junction transistor(North junction of NpN)
Collector
Bus interface unit
Balanced Bridge
ANSI
40. Describes a number system with a base of ten
Bleeder Current
Decimal
Circuit
TTL
41. The application of a dc voltage to an electronic device to produce a desired mode of operation
Collector
Bias
TTL
Balanced Bridge
42. A filter that rejects a range of frequencies lying between two critical frequencies and passes frequencies above and below that range.
Kirchoff's Voltage Law
TTL
Band- stop filter
Controller
43. An expression of variables and operators used to express the operation of a logic circuit
Binary
Base
Capacitor
Boolean expression
44. Burst extended data output dynamic random- access memory
BEDO DRAM
Ampere- hour(Ah) rating
Capacitor
Capacity
45. A logic circuit used to add two binary numbers
BIOS
AND
Adder
bed- of- nails
46. A bridge circuit that is in the balanced state as indicated by 0 V across the output.
Astable
Amplitude
Balanced Bridge
Clock
47. Characterized by ten states or values
Dual in - line package
Decrement
Balanced Load
Decade
48. A condition where all the load currents are equal and the neutral current is zero
Bus interface unit
Balanced Load
Decade Counter
Central processing unit
49. The digit generated when the sum of two binary digits exceeds 1
Balanced Bridge
Bandwidth
Carry
Adder
50. Digital audio tape; a type of magnetic tape format
Angular Velocity
Bistable
DAT
Closed circuit